www.pudn.com > FPGA-can_1553b.rar > mancodec.tdf, change:2011-04-08,size:866b


library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
	entity m_code is 
	port( clk : in std_logic; --系统时钟输入 
	databin : in std_logic; --基带信号输入 
	datamout : out std_logic); --曼彻斯特编码输出 
	end m_code; 
architecture behave of m_code is 
--con为曼彻斯特码型寄存器,值为"01"或是"10" 
signal con : std_logic_vector(1 downto 0); 	 
signal flag : std_logic; --并串转化信号量 
begin 
	--曼彻斯特码型转化进程 
	process(clk) 
	beginif clk'event and clk = '1' then 
	if flag = '0' then 
	if databin = '1' then 
	con <= "10"; 
	else 
	con <= "01"; 
	end if; 
	end if; 
	end if; 
	end process; 
	--并串转化和曼彻斯特编码输出进程 
	process(clk)begin 
	if clk'event and clk = '1' thenif flag = '1' then 
	datamout <= con(1); 
	flag <= not flag; 
	elsedatamout <= con(0); 
	flag <= not flag; 
	end if; 
	end if; 
	end process; 
end behave;