www.pudn.com > SHA1.zip > sha_1_2.v, change:2001-02-09,size:5887b


`include "add_32.v" 
`include "add_32_5_csa.v" 
`include "buffer_32.v" 
`include "input_672.v" 
`include "mux_1.v" 
`include "mux_2.v" 
`include "mux_3.v" 
`include "mux_wt.v" 
`include "shift_30.v" 
`include "shift_5.v" 
`include "wt.v" 
`include "f_1.v" 
`include "f_2.v" 
`include "f_3.v" 
`include "f_4.v" 
`include "k.v" 
`include "control.v" 
 
module sha_1_2 (in, reset, clock, out_1_0, out_1_1, out_1_2, out_1_3, out_1_4); 
 
  
	input clock, reset; 
	input [7:0] in; 
 
	output [31:0] out_1_0, out_1_1, out_1_2, out_1_3, out_1_4; 
	 
	wire [31:0] out_0_0, out_0_1, out_0_2, out_0_3, out_0_4,  out_wt; 
	wire hold_672, hold_0, hold_1, hold_2, hold_3, hold_4, hold_5, hold_6, hold_7, hold_8, hold_9; 
	wire hold_10, hold_11, hold_12, hold_13, hold_14, hold_15; 
	wire hold_1_0, hold_1_1, hold_1_2, hold_1_3, hold_1_4, sel_1, sel_3; 
	wire [3:0] sel, sel_2; 
	wire [1:0] sel_4; 
	 
	wire [671:0] wire_672; 
	wire [31:0] wire_32_0, wire_32_1, wire_32_2, wire_32_3, wire_32_4, wire_32_5; 
	wire [31:0] wire_32_6, wire_32_7, wire_32_8, wire_32_9, wire_32_10; 
	wire [31:0] wire_32_11, wire_32_12, wire_32_13, wire_32_14, wire_32_15; 
	wire [31:0] wire_32_16, wire_32_17, wire_32_18, wire_32_19, wire_32_20; 
	wire [31:0] wire_32_21, wire_32_22, wire_32_23, wire_32_24, wire_32_25; 
	wire [31:0] wire_32_26, wire_32_27, wire_32_28, wire_32_29, wire_32_30; 
	wire [31:0] wire_32_31, wire_32_32; 
	wire [31:0] wire_32_33, wire_32_34, wire_32_35, wire_32_36, wire_32_37; 
	wire [31:0] wire_32_43, wire_32_44, wire_32_45, wire_32_46, wire_32_47; 
	wire [31:0] wire_32_48, wire_32_50, wire_32_51, wire_32_52; 
	wire [127:0] wire_128; 
 
	control control (clock, reset, 	sel_1, sel_2, sel_3, sel_4, sel, hold_672, hold_15, hold_14, hold_13, hold_12, hold_11, hold_10, hold_9, hold_8, hold_7, hold_6, hold_5, hold_4, hold_3, hold_2, hold_1, hold_0, hold_1_4, hold_1_3, hold_1_2, hold_1_1, hold_1_0); 
	 
	input_672 input_672 (in, clock, hold_672, wire_672); 
	 
	mux_2 u_0 (wire_672[31:0],	    wire_32_32   , sel_1, wire_32_0); 
	mux_2 u_1 (wire_672[63:32],	    wire_32_32   , sel_1, wire_32_1); 
	mux_2 u_2 (wire_672[95:64],     wire_32_32   , sel_1, wire_32_2); 
	mux_2 u_3 (wire_672[127:96],    wire_32_32   , sel_1, wire_32_3); 
	mux_2 u_4 (wire_672[159:128],   wire_32_32   , sel_1, wire_32_4); 
	mux_2 u_5 (wire_672[191:160],   wire_32_32 , sel_1, wire_32_5); 
	mux_2 u_6 (wire_672[223:192],   wire_32_32 , sel_1, wire_32_6); 
	mux_2 u_7 (wire_672[255:224],   wire_32_32 , sel_1, wire_32_7); 
	mux_2 u_8 (wire_672[287:256],   wire_32_32 , sel_1, wire_32_8); 
	mux_2 u_9 (wire_672[319:288],   wire_32_32 , sel_1, wire_32_9); 
	mux_2 u_10 (wire_672[351:320],  wire_32_32 , sel_1, wire_32_10); 
	mux_2 u_11 (wire_672[383:352],  wire_32_32 , sel_1, wire_32_11); 
	mux_2 u_12 (wire_672[415:384],  wire_32_32 , sel_1, wire_32_12); 
	mux_2 u_13 (wire_672[447:416],  wire_32_32 , sel_1, wire_32_13); 
	mux_2 u_14 (wire_672[479:448],  wire_32_32 , sel_1, wire_32_14); 
	mux_2 u_15 (wire_672[511:480],  wire_32_32 , sel_1, wire_32_15); 
	 
	buffer_32 v_0 (wire_32_0, clock, hold_0, wire_32_16); 
	buffer_32 v_1 (wire_32_1, clock, hold_1, wire_32_17); 
	buffer_32 v_2 (wire_32_2, clock, hold_2, wire_32_18); 
	buffer_32 v_3 (wire_32_3, clock, hold_3, wire_32_19); 
	buffer_32 v_4 (wire_32_4, clock, hold_4, wire_32_20); 
	buffer_32 v_5 (wire_32_5, clock, hold_5, wire_32_21); 
	buffer_32 v_6 (wire_32_6, clock, hold_6, wire_32_22); 
	buffer_32 v_7 (wire_32_7, clock, hold_7, wire_32_23); 
	buffer_32 v_8 (wire_32_8, clock, hold_8, wire_32_24); 
	buffer_32 v_9 (wire_32_9, clock, hold_9, wire_32_25); 
	buffer_32 v_10 (wire_32_10, clock, hold_10, wire_32_26); 
	buffer_32 v_11 (wire_32_11, clock, hold_11, wire_32_27); 
	buffer_32 v_12 (wire_32_12, clock, hold_12, wire_32_28); 
	buffer_32 v_13 (wire_32_13, clock, hold_13, wire_32_29); 
	buffer_32 v_14 (wire_32_14, clock, hold_14, wire_32_30); 
	buffer_32 v_15 (wire_32_15, clock, hold_15, wire_32_31); 
	 
 
	mux_wt mux_wt ({wire_32_31, wire_32_30, wire_32_29, wire_32_28, wire_32_27, wire_32_26, wire_32_25, wire_32_24, wire_32_23, wire_32_22, wire_32_21, wire_32_20, wire_32_19, wire_32_18, wire_32_17, wire_32_16}, sel, wire_128); 
	wt wt (wire_128[127:96], wire_128[95:64], wire_128[63:32], wire_128[31:0], wire_32_32); 
	mux_3 mux_3 ({wire_32_31, wire_32_30, wire_32_29, wire_32_28, wire_32_27, wire_32_26, wire_32_25, wire_32_24, wire_32_23, wire_32_22, wire_32_21, wire_32_20, wire_32_19, wire_32_18, wire_32_17, wire_32_16}, sel_2, out_wt); 
 
		 
	mux_2 a_0 (wire_672[543:512],   wire_32_51, sel_3, wire_32_33); 
	mux_2 a_1 (wire_672[575:544],	out_0_0,   	sel_3, wire_32_34); 
	mux_2 a_2 (wire_672[607:576],  	wire_32_52, sel_3, wire_32_35); 
	mux_2 a_3 (wire_672[639:608],  	out_0_2,   	sel_3, wire_32_36); 
	mux_2 a_4 (wire_672[671:640],	out_0_3,   	sel_3, wire_32_37); 
	 
	buffer_32 c_0 (wire_32_33, clock, hold_1_0, out_0_0); 
	buffer_32 c_1 (wire_32_34, clock, hold_1_1, out_0_1); 
	buffer_32 c_2 (wire_32_35, clock, hold_1_2, out_0_2); 
	buffer_32 c_3 (wire_32_36, clock, hold_1_3, out_0_3); 
	buffer_32 c_4 (wire_32_37, clock, hold_1_4, out_0_4); 
	 
	f_1 f_1 (out_0_1, out_0_2, out_0_3, wire_32_43); 
	f_2 f_2 (out_0_1, out_0_2, out_0_3, wire_32_44);	 
	f_3 f_3 (out_0_1, out_0_2, out_0_3, wire_32_45); 
	f_4 f_4 (out_0_1, out_0_2, out_0_3, wire_32_46); 
 
	mux_1 mux_1 (wire_32_43, wire_32_44, wire_32_45, wire_32_46, sel_4, wire_32_47); 
	shift_5 shift_5 (out_0_0, wire_32_48); 
	k k (sel_4, wire_32_50); 
	 
	add_32_5_csa add_32_5_csa (out_wt, out_0_4, wire_32_50, wire_32_48, wire_32_47, 	wire_32_51); 
	shift_30 shift_30 (out_0_1, wire_32_52); 
 
	add_32 d_1 (wire_672[543:512], out_0_0, out_1_0); 
	add_32 d_2 (wire_672[575:544], out_0_1, out_1_1); 
	add_32 d_3 (wire_672[607:576], out_0_2, out_1_2); 
	add_32 d_4 (wire_672[639:608], out_0_3, out_1_3); 
	add_32 d_5 (wire_672[671:640], out_0_4, out_1_4); 
 
endmodule