www.pudn.com > SHA1.zip > f_1.v, change:2001-01-06,size:221b


module F_1 (b, c, d, 	out); 
 
	input [31:0] b, c, d; 
	output [31:0] out; 
 
	 
	wire [31:0] w_1, w_2, w_3; 
 
 
	assign w_1 = b & c; 
	assign w_2 = ~ b; 
	assign w_3 = w_2 & d; 
	assign out = w_1 | w_3; 
 
endmodule