www.pudn.com > yy.zip > seg7d.vhd, change:2010-12-06,size:459b


LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
 
ENTITY seg7d IS 
PORT(clk,reset: IN STD_LOGIC; 
     sm5: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END seg7d; 
 
ARCHITECTURE behav OF seg7d IS 
SIGNAL data:STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN 
  PROCESS(clk) 
  BEGIN 
    IF reset='0' THEN 
       data<="0000"; 
    ELSIF (clk'EVENT AND clk='1') THEN  
      data<=data+1; 
    END IF; 
  END PROCESS; 
sm5<=data; 
END behav;