www.pudn.com > PS2_jianpanshibie_FPGA.rar > reset_generate.v, change:2010-12-02,size:427b


module reset_generate(clk,rstn); 
input clk; 
output rstn; 
reg rstn; 
 
parameter	COUNT_START = 8'd100, 
			COUNT_END = 8'd10; 
 
reg[7:0] cnt_0=COUNT_START; 
always @ (posedge clk) 
begin 
	if(cnt_0==COUNT_END) 
		begin 
			cnt_0<=COUNT_END; 
			rstn<=1'b1; 
		end 
	else if(cnt_0<COUNT_END) 
		begin 
			cnt_0<=cnt_0+8'd1; 
			rstn<=1'b0; 
		end 
	else 
		begin 
			cnt_0<=cnt_0+1'b1; 
			rstn<=1'b1; 
		end 
end 
endmodule