www.pudn.com > PS2_jianpanshibie_FPGA.rar > ps2_decode.v, change:2010-12-03,size:1926b


module ps2_decode (clk,rstn,h2l_sig,ps2_data_pin_in,ps2_data_f,ps2_data_s,ps2_data_t,ps2_done_sig); 
input clk; 
input rstn; 
input h2l_sig; 
input ps2_data_pin_in; 
output [7:0] ps2_data_f,ps2_data_s,ps2_data_t; 
output ps2_done_sig; 
 
reg [7:0] first_rdata; 
reg [7:0] second_rdata; 
reg [7:0] third_rdata; 
reg [5:0] i; 
reg isshift; 
reg isdone; 
always @(posedge clk or negedge rstn) 
	if(!rstn) 
		begin 
			first_rdata<=8'd0; 
			second_rdata<=8'd0; 
			third_rdata<=8'd0; 
			i<=6'd0; 
			isdone<=1'b0; 
		end 
	else 
		case (i) 
			6'd0:if(h2l_sig) i<=i+1'b1; 
			6'd1,6'd2,6'd3,6'd4,6'd5,6'd6,6'd7,6'd8: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
						first_rdata[i-1]<=ps2_data_pin_in; 
					end 
			6'd9,6'd10: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
					end 
			6'd11: 
				if(first_rdata==8'hf0 | first_rdata==8'he0) i<=i+1'b1; 
				else 
					begin 
						i<=6'd35; 
						second_rdata<=8'd0; 
						third_rdata<=8'd0; 
					end 
			 
			6'd12:if(h2l_sig) i<=i+1'b1; 
			6'd13,6'd14,6'd15,6'd16,6'd17,6'd18,6'd19,6'd20: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
						second_rdata[i-13]<=ps2_data_pin_in; 
					end 
			6'd21,6'd22: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
					end 
			6'd23: 
				if(second_rdata==8'hf0) i<=i+1'b1; 
				else 
					begin 
						i<=6'd35; 
						third_rdata<=8'd0; 
					end 
			 
			6'd24:if(h2l_sig) i<=i+1'b1; 
			6'd25,6'd26,6'd27,6'd28,6'd29,6'd30,6'd31,6'd32: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
						third_rdata[i-25]<=ps2_data_pin_in; 
					end 
			6'd33,6'd34: 
				if(h2l_sig) 
					begin 
						i<=i+1'b1; 
					end 
			 
			6'd35: 
				begin 
					i<=i+1'b1; 
					isdone<=1'b1; 
				end 
			6'd36: 
				begin 
					i<=6'd0; 
					isdone<=1'b0; 
				end 
		endcase 
 
assign ps2_data_f = first_rdata; 
assign ps2_data_s = second_rdata; 
assign ps2_data_t = third_rdata; 
assign ps2_done_sig = isdone; 
 
endmodule