www.pudn.com > PS2_jianpanshibie_FPGA.rar > edge_detect.v, change:2010-12-02,size:375b


module edge_detect (clk,rstn,ps2_clk_in,h2l_sig); 
input clk; 
input rstn; 
input ps2_clk_in; 
output h2l_sig; 
 
reg h2l_f1; 
reg h2l_f2; 
always @(posedge clk or negedge rstn) 
begin 
	if(!rstn) 
		begin 
			h2l_f1<=1'b1; 
			h2l_f2<=1'b1; 
		end 
	else 
		begin 
			h2l_f1<=ps2_clk_in; 
			h2l_f2<=h2l_f1; 
		end 
end 
 
assign h2l_sig = h2l_f2 & (!h2l_f1); 
 
endmodule