www.pudn.com > PS2_jianpanshibie_FPGA.rar > top.hif, change:2010-12-03,size:2967b


Version 9.0 Build 132 02/25/2009 SJ Full Version 
41 
2959 
OFF 
OFF 
OFF 
ON 
ON 
ON 
FV_OFF 
Level2 
0 
0 
VRSM_ON 
VHSM_ON 
0 
-- Start Library Paths -- 
-- End Library Paths -- 
-- Start VHDL Libraries -- 
-- End VHDL Libraries -- 
# entity 
reset_generate 
# storage 
db|top.(2).cnf 
db|top.(2).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
reset_generate.v 
d5ccfc59c97f75fa5b6749c557853d 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# user_parameter { 
COUNT_START 
01100100 
PARAMETER_UNSIGNED_BIN 
DEF 
COUNT_END 
00001010 
PARAMETER_UNSIGNED_BIN 
DEF 
} 
# hierarchies { 
reset_generate:inst5 
} 
# macro_sequence 
 
# end 
# entity 
ps2_module 
# storage 
db|top.(3).cnf 
db|top.(3).cnf 
# case_insensitive 
# source_file 
ps2_module.bdf 
3cd6f32a9872667655c7f97a0bbf86d 
26 
# internal_option { 
BLOCK_DESIGN_NAMING 
AUTO 
} 
# hierarchies { 
ps2_module:inst2 
} 
# macro_sequence 
 
# end 
# entity 
ps2_decode 
# storage 
db|top.(4).cnf 
db|top.(4).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
ps2_decode.v 
f167d77043cda0cffb1e961e6c6d968f 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# hierarchies { 
ps2_module:inst2|ps2_decode:inst1 
} 
# macro_sequence 
 
# end 
# entity 
edge_detect 
# storage 
db|top.(5).cnf 
db|top.(5).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
edge_detect.v 
e78f8b89c0f7c5b345933c2317246e2 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# hierarchies { 
ps2_module:inst2|edge_detect:inst 
} 
# macro_sequence 
 
# end 
# entity 
top 
# storage 
db|top.(0).cnf 
db|top.(0).cnf 
# case_insensitive 
# source_file 
top.bdf 
2a344afd7e67fa90e8d8ea77c0f34e37 
26 
# internal_option { 
BLOCK_DESIGN_NAMING 
AUTO 
} 
# hierarchies { 
| 
} 
# macro_sequence 
 
# end 
# entity 
cmd_control 
# storage 
db|top.(1).cnf 
db|top.(1).cnf 
# logic_option { 
AUTO_RAM_RECOGNITION 
ON 
} 
# case_sensitive 
# source_file 
cmd_control.v 
b0cffd81873b33bcf079ff17947f3534 
8 
# internal_option { 
HDL_INITIAL_FANOUT_LIMIT 
OFF 
AUTO_RESOURCE_SHARING 
OFF 
AUTO_RAM_RECOGNITION 
ON 
AUTO_ROM_RECOGNITION 
ON 
IGNORE_VERILOG_INITIAL_CONSTRUCTS 
OFF 
VERILOG_CONSTANT_LOOP_LIMIT 
5000 
VERILOG_NON_CONSTANT_LOOP_LIMIT 
250 
} 
# hierarchies { 
cmd_control:inst 
} 
# macro_sequence 
 
# end 
# complete