www.pudn.com > PS2_jianpanshibie_FPGA.rar > mux_0hc.tdf, change:2010-12-02,size:6954b
--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Cyclone" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=32 LPM_WIDTH=1 LPM_WIDTHS=5 data result sel --VERSION_BEGIN 9.0 cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ VERSION_END -- Copyright (C) 1991-2009 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. --synthesis_resources = lut 21 SUBDESIGN mux_0hc ( data[31..0] : input; result[0..0] : output; sel[4..0] : input; ) VARIABLE result_node[0..0] : WIRE; sel_ffs_wire[9..0] : WIRE; sel_node[4..0] : WIRE; w_data124w[3..0] : WIRE; w_data125w[3..0] : WIRE; w_data126w[3..0] : WIRE; w_data127w[3..0] : WIRE; w_data12w[31..0] : WIRE; w_data227w[3..0] : WIRE; w_data228w[3..0] : WIRE; w_data229w[3..0] : WIRE; w_data230w[3..0] : WIRE; w_sel115w[3..0] : WIRE; w_sel128w[1..0] : WIRE; w_sel231w[1..0] : WIRE; BEGIN result[] = result_node[]; result_node[] = ( ((sel_node[4..4] & ((((((w_data228w[1..1] & w_sel231w[0..0]) & (! (((w_data228w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data228w[2..2]))))) # ((((w_data228w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data228w[2..2]))) & (w_data228w[3..3] # (! w_sel231w[0..0])))) & w_sel115w[2..2]) & (! ((((((w_data227w[1..1] & w_sel231w[0..0]) & (! (((w_data227w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data227w[2..2]))))) # ((((w_data227w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data227w[2..2]))) & (w_data227w[3..3] # (! w_sel231w[0..0])))) & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # (((w_data229w[1..1] & w_sel231w[0..0]) & (! (((w_data229w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data229w[2..2]))))) # ((((w_data229w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data229w[2..2]))) & (w_data229w[3..3] # (! w_sel231w[0..0]))))))))) # (((((((w_data227w[1..1] & w_sel231w[0..0]) & (! (((w_data227w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data227w[2..2]))))) # ((((w_data227w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data227w[2..2]))) & (w_data227w[3..3] # (! w_sel231w[0..0])))) & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # (((w_data229w[1..1] & w_sel231w[0..0]) & (! (((w_data229w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data229w[2..2]))))) # ((((w_data229w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data229w[2..2]))) & (w_data229w[3..3] # (! w_sel231w[0..0]))))))) & ((((w_data230w[1..1] & w_sel231w[0..0]) & (! (((w_data230w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data230w[2..2]))))) # ((((w_data230w[0..0] & (! w_sel231w[1..1])) & (! w_sel231w[0..0])) # (w_sel231w[1..1] & (w_sel231w[0..0] # w_data230w[2..2]))) & (w_data230w[3..3] # (! w_sel231w[0..0])))) # (! w_sel115w[2..2]))))) # ((! sel_node[4..4]) & ((((((w_data125w[1..1] & w_sel128w[0..0]) & (! (((w_data125w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data125w[2..2]))))) # ((((w_data125w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data125w[2..2]))) & (w_data125w[3..3] # (! w_sel128w[0..0])))) & w_sel115w[2..2]) & (! ((((((w_data124w[1..1] & w_sel128w[0..0]) & (! (((w_data124w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data124w[2..2]))))) # ((((w_data124w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data124w[2..2]))) & (w_data124w[3..3] # (! w_sel128w[0..0])))) & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # (((w_data126w[1..1] & w_sel128w[0..0]) & (! (((w_data126w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data126w[2..2]))))) # ((((w_data126w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data126w[2..2]))) & (w_data126w[3..3] # (! w_sel128w[0..0]))))))))) # (((((((w_data124w[1..1] & w_sel128w[0..0]) & (! (((w_data124w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data124w[2..2]))))) # ((((w_data124w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data124w[2..2]))) & (w_data124w[3..3] # (! w_sel128w[0..0])))) & (! w_sel115w[3..3])) & (! w_sel115w[2..2])) # (w_sel115w[3..3] & (w_sel115w[2..2] # (((w_data126w[1..1] & w_sel128w[0..0]) & (! (((w_data126w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data126w[2..2]))))) # ((((w_data126w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data126w[2..2]))) & (w_data126w[3..3] # (! w_sel128w[0..0]))))))) & ((((w_data127w[1..1] & w_sel128w[0..0]) & (! (((w_data127w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data127w[2..2]))))) # ((((w_data127w[0..0] & (! w_sel128w[1..1])) & (! w_sel128w[0..0])) # (w_sel128w[1..1] & (w_sel128w[0..0] # w_data127w[2..2]))) & (w_data127w[3..3] # (! w_sel128w[0..0])))) # (! w_sel115w[2..2]))))))); sel_ffs_wire[] = ( sel_ffs_wire[4..0], sel[4..0]); sel_node[] = ( sel_ffs_wire[9..9], sel_ffs_wire[3..2], sel[1..0]); w_data124w[3..0] = w_data12w[3..0]; w_data125w[3..0] = w_data12w[7..4]; w_data126w[3..0] = w_data12w[11..8]; w_data127w[3..0] = w_data12w[15..12]; w_data12w[] = ( data[31..0]); w_data227w[3..0] = w_data12w[19..16]; w_data228w[3..0] = w_data12w[23..20]; w_data229w[3..0] = w_data12w[27..24]; w_data230w[3..0] = w_data12w[31..28]; w_sel115w[3..0] = sel_node[3..0]; w_sel128w[1..0] = sel_node[1..0]; w_sel231w[1..0] = sel_node[1..0]; END; --VALID FILE