www.pudn.com > interlace.rar > interlace.v, change:2010-11-10,size:5051b

`timescale 1ns / 1ps 
////////////////////////////////////////////////////////////////////////////////// 
// Company:  
// Engineer:  
//  
// Create Date:    14:50:54 11/08/2010  
// Design Name:  
// Module Name:    interlace  
// Project Name:  
// Target Devices:  
// Tool versions:  
// Description:  
// 
// Dependencies:  
// 
// Revision:  
// Revision 0.01 - File Created 
// Additional Comments:  
// 
////////////////////////////////////////////////////////////////////////////////// 
module interlace( 
						//input 
						clk, 
						rst, 
						data_in, 
						nd, 
						//output 
						data_out, 
						rdy				 
					 ); 
//parameter 
parameter ping= 1'd0; 
parameter pong= 1'd1; 
parameter frame_len= 7'd100; 
 
//input&output					  
input clk; 
input rst; 
input [15:0] data_in; 
input nd; 
output [15:0] data_out; 
output rdy; 
reg [15:0] data_out; 
reg rdy; 
 
//inter_rom 
reg [6:0] addr; 
wire [15:0] dout; 
 
//inter_ram_ping 
reg wea_pi;  
reg [6:0] addra_pi;  
reg [15:0] dina_pi; 
reg [6:0] addrb_pi;  
wire [15:0] doutb_pi; 
 
//inter_ram_pong 
reg wea_po;  
reg [6:0] addra_po;  
reg [15:0] dina_po; 
reg [6:0] addrb_po;  
wire [15:0] doutb_po; 
 
//in modules 
reg nd_reg; 
reg [15:0] data_in_reg; 
reg flag; 
reg flag_reg; 
 
reg full_ping; 
reg full_pong; 
 
reg [7:0] full_cnt_pi; 
reg [7:0] full_cnt_po; 
 
reg data_en; 
 
inter_rom u_inter_rom ( 
								.clka(clk), 
								.addra(addr), // Bus [6 : 0]  
								.douta(dout)	// Bus [15 : 0]  
								);  
			 
inter_ram u_inter_ram_ping ( 
									.clka(clk), 
									.wea(wea_pi), // Bus [0 : 0]  
									.addra(addra_pi), // Bus [6 : 0]  
									.dina(dina_pi), // Bus [15 : 0]  
									.clkb(clk), 
									.rstb(~rst), 
									.addrb(addrb_pi), // Bus [6 : 0]  
									.doutb(doutb_pi) // Bus [15 : 0]  
									);  
	 
inter_ram u_inter_ram_pong ( 
									.clka(clk), 
									.wea(wea_po), // Bus [0 : 0]  
									.addra(addra_po), // Bus [6 : 0]  
									.dina(dina_po), // Bus [15 : 0]  
									.clkb(clk), 
									.rstb(~rst), 
									.addrb(addrb_po), // Bus [6 : 0]  
									.doutb(doutb_po) // Bus [15 : 0]  
									); 
 
always @(posedge clk)  
begin 
	if(!rst)  
		begin 
			nd_reg 		<= 1'd0; 
			data_in_reg <= 1'd0; 
			addr 			<= 7'd0; 
			flag 			<= 1'd0; 
			flag_reg 	<= 1'd0; 
			full_cnt_pi <= 1'd0; 
			full_cnt_po <= 1'd0; 
			full_ping 	<= 1'd0; 
			full_pong 	<= 1'd0; 
		end 
	else 
		begin 
			nd_reg 		<= nd; 
			data_in_reg <= data_in; 
			flag_reg 	<= flag; 
			if(nd)  
				begin 
					if(addr < frame_len - 1'd1)  
						begin 
							addr <= addr + 1'd1; 
						end 
					else  
						begin 
							addr <= 1'd0; 
							flag <= ~flag; 
							if(flag == ping) 
								full_ping <= 1'd1; 
							else 
								full_pong <= 1'd1; 
						end					 
				end 
			if(full_ping) 
				begin 
					if(full_cnt_pi < frame_len - 1'd1) 
						begin 
							full_cnt_pi <= full_cnt_pi + 1'd1; 
						end 
					else 
						begin 
							full_cnt_pi <= 1'd0; 
							full_ping	<= 1'd0; 
						end 
				end 
			if(full_pong) 
				begin 
					if(full_cnt_po < frame_len - 1'd1) 
						begin 
							full_cnt_po <= full_cnt_po + 1'd1; 
						end 
					else 
						begin 
							full_cnt_po <= 1'd0; 
							full_pong	<= 1'd0; 
						end 
				end 
		 
		end 
end 
 
always @(posedge clk) //写入乒乓ram中 
begin 
	if(!rst) 
		begin 
			wea_pi 	<= 1'd0; 
			addra_pi <= 7'd0; 
			dina_pi 	<= 1'd0; 
			wea_po 	<= 1'd0; 
			addra_po <= 7'd0; 
			dina_po 	<= 1'd0; 
		end 
	else 
		begin 
			if(flag_reg == ping) 
				begin 
					if(nd_reg) 
						begin 
							wea_po 	<= 1'd0; 
							wea_pi 	<= 1'd1; 
							addra_pi <= dout; 
							dina_pi 	<= data_in_reg; 
						end 
					else 
						begin 
							wea_pi 	<= 1'd0; 
						end 
				end 
			else 
				begin 
					if(nd_reg) 
						begin 
							wea_pi 	<= 1'd0; 
							wea_po 	<= 1'd1; 
							addra_po <= dout; 
							dina_po 	<= data_in_reg; 
						end 
					else 
						begin 
							wea_po 	<= 1'd0; 
						end 
				end 
		end 
end 
 
always @(posedge clk) 
begin 
	if(!rst) 
		begin 
			addrb_pi <= 1'd0; 
			addrb_po <= 1'd0; 
			rdy 		<= 1'd0; 
			data_out <= 1'd0; 
			data_en	<= 1'd0; 
		end 
	else 
		begin 
			if(full_ping || full_pong) 
				begin 
					if(full_ping) 
						begin 
							addrb_po <= 1'd0; 
							if(addrb_pi < frame_len - 1'd1)									 
								addrb_pi <= addrb_pi + 1'd1; 
							data_en 	<= 1'd1;			 
						end 
					else 
						begin 
							addrb_pi <= 1'd0; 
							if(addrb_po < frame_len - 1'd1)									 
								addrb_po <= addrb_po + 1'd1; 
							data_en 	<= 1'd1;		 
						end 
				end 
			else 
				begin 
					data_en 	<= 1'd0;	 
					addrb_pi <=	1'd0;		 
					addrb_po <=	1'd0;						 
				end 
				 
			if(data_en) 
				begin 
					rdy		<= 1'd1; 
					if(addrb_pi != 1'd0) 
						begin 
							data_out <= doutb_pi; 
						end 
					if(addrb_po != 1'd0) 
						begin 
							data_out <= doutb_po; 
						end 
				end 
			else 
				begin 
					rdy <= 1'd0; 
				end 
		end 
end 
 
 
	  
 
									 
 
endmodule