www.pudn.com > NiosII_LED.rar > setup_sim.do, change:2010-10-27,size:5870b


    set sopc "d:/altera/90/quartus//sopc_builder" 
    set sopc_perl "d:/altera/90/quartus//bin/perl" 
    echo "Sopc_Builder Directory: $sopc"; 
 
# ModelSimPE and OEM have different requirements 
# regarding how they simulate their test bench. 
# We account for that here. 
if { [ string match "*ModelSim ALTERA*" [ vsim -version ] ] } { 
 alias _init_setup {vlib work 
                       vmap altera               work 
                       vmap stratixiv_hssi       work 
                       vmap arriaii_hssi         work 
                       vmap stratixiv_pcie_hip   work 
                       vmap arriaii_pcie_hip     work 
                       vcom -93 -explicit d:/altera/90/quartus/libraries/vhdl/altera/altera_europa_support_lib.vhd 
		       } } else { 
 alias _init_setup {vlib work 
                       vmap altera               work 
                       vmap stratixiv_hssi       work 
                       vmap arriaii_hssi         work 
                       vmap stratixiv_pcie_hip   work 
                       vmap arriaii_pcie_hip     work 
                       vmap lpm                  work 
                       vmap altera_mf            work 
                       vmap sgate_pack           work 
                       vmap sgate                work 
                       vmap stratixiigx_hssi     work 
                       vmap arriagx_hssi         work 
                       vmap stratixgx_hssi       work 
                       vmap altgxb_lib           work 
                       vcom -93 -explicit d:/altera/90/quartus/libraries/vhdl/altera/altera_europa_support_lib.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/altera_mf_components.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/altera_mf.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/220pack.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/220model.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/sgate_pack.vhd 
                       vcom -93 -explicit d:/altera/90/quartus/eda/sim_lib/sgate.vhd 
                       } }  
 
 
# ModelSimPE and OEM have different requirements 
# regarding how they simulate their test bench. 
# We account for that here. 
if { [ string match "*ModelSim ALTERA*" [ vsim -version ] ] } { 
 alias _vsim {vsim -t ps +nowarnTFMPC  -L lpm -L altera -L altera_mf -L sgate test_bench }  } else { 
 alias _vsim {vsim -t ps +nowarnTFMPC test_bench }  }  
 
alias test_contents_files {if {[ file exists "contents_file_warning.txt" ]} { set ch [open "contents_file_warning.txt" r];  while { 1 } { if ([eof $ch]) {break}; gets $ch line; puts $line; }; close $ch; } } 
alias s "_init_setup 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/pio_led.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/epcs.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_test_bench.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_mult_cell.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_oci_test_bench.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_jtag_debug_module_tck.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_jtag_debug_module_sysclk.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu_jtag_debug_module_wrapper.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/cpu.vho 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/sysid.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/jtag_uart.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/sdram.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/sdram_test_component.vhd 
vcom -93 -explicit E:/FPGA_System/Altera/NiosII_LED/CPU_LED.vhd 
_vsim 
do virtuals.do 
set StdArithNoWarnings 1 
; test_contents_files" 
alias r "exec $sopc_perl/bin/perl -I $sopc/bin/perl_lib -I $sopc/bin $sopc/bin/run_command_in_unix_like_shell.pl $sopc { cd ../;  ./CPU_LED_generation_script  } " 
alias c "echo {Regenerating memory contents. 
 (This may take a moment)...}; restart -f; exec $sopc_perl/bin/perl -I $sopc/bin/perl_lib -I $sopc/bin $sopc/bin/run_command_in_unix_like_shell.pl $sopc { cd ../;  ./CPU_LED_generation_script  }  --software_only=1" 
alias w "do wave_presets.do" 
alias l "do list_presets.do" 
alias jtag_uart_log "./jtag_uart_log.bat $sopc_perl/bin &" 
alias h " 
echo @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 
echo @@ 
echo @@        setup_sim.do 
echo @@ 
echo @@   Defined aliases: 
echo @@ 
echo @@   s  -- Load all design (HDL) files. 
echo @@           re-vlog/re-vcom and re-vsim the design. 
echo @@ 
echo @@   c  -- Re-compile memory contents. 
echo @@          Builds C- and assembly-language programs 
echo @@          (and associated simulation data-files 
echo @@          such as UART simulation strings) for 
echo @@          refreshing memory contents. 
echo @@          Does NOT re-generate hardware (HDL) files 
echo @@          ONLY WORKS WITH LEGACY SDK (Not the Nios IDE) 
echo @@ 
echo @@   w  -- Sets-up waveforms for this design 
echo @@          Each SOPC-Builder component may have 
echo @@          signals 'marked' for display during 
echo @@          simulation.  This command opens a wave- 
echo @@          window containing all such signals. 
echo @@ 
echo @@   l  -- Sets-up list waveforms for this design 
echo @@          Each SOPC-Builder component may have 
echo @@          signals 'marked' for listing during 
echo @@          simulation.  This command opens a list- 
echo @@          window containing all such signals. 
echo @@ 
echo @@   jtag_uart_log  -- display interactive output window for jtag_uart 
 
echo @@ 
echo @@   h  -- print this message  
echo @@ 
echo @@ ***Special VHDL settings*** 
echo @@    StdArithNoWarnings=1 in s command 
echo @@" 
 
h