www.pudn.com > NiosII_LED.rar > CPU_LED_log.txt, change:2010-10-27,size:3790b


Altera SOPC Builder Version 9.00 Build 132 
Copyright (c) 1999-2009 Altera Corporation.  All rights reserved. 
 
 
# 2010.10.27 23:07:42 (*) mk_custom_sdk starting 
# 2010.10.27 23:07:42 (*) Reading project E:/FPGA_System/Altera/NiosII_LED/CPU_LED.ptf. 
 
# 2010.10.27 23:07:42 (*) Finding all CPUs 
# 2010.10.27 23:07:42 (*) Finding all available components 
# 2010.10.27 23:07:42 (*) Reading E:/FPGA_System/Altera/NiosII_LED/.sopc_builder/install.ptf 
 
# 2010.10.27 23:07:42 (*) Found 67 components 
 
# 2010.10.27 23:07:43 (*) Finding all peripherals 
 
# 2010.10.27 23:07:43 (*) Finding software components 
 
# 2010.10.27 23:07:44 (*) (Legacy SDK Generation Skipped) 
# 2010.10.27 23:07:44 (*) (All TCL Script Generation Skipped) 
# 2010.10.27 23:07:44 (*) (No Libraries Built) 
# 2010.10.27 23:07:44 (*) (Contents Generation Skipped) 
# 2010.10.27 23:07:44 (*) mk_custom_sdk finishing 
 
# 2010.10.27 23:07:44 (*) Starting generation for system: CPU_LED. 
 
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# 2010.10.27 23:07:46 (*) Running Generator Program for cpu 
 
# 2010.10.27 23:07:47 (*)   IP functional simulation model enabled: Uncheck System Generation Simulation box for faster generation if HDL Simulation not required. 
# 2010.10.27 23:07:49 (*)   Checking for plaintext license. 
# 2010.10.27 23:07:53 (*)   Plaintext license not found. 
# 2010.10.27 23:07:53 (*)   Checking for encrypted license (non-evaluation). 
# 2010.10.27 23:07:54 (*)   Encrypted license found.  SOF will not be time-limited. 
# 2010.10.27 23:07:54 (*)   Getting CPU configuration settings 
# 2010.10.27 23:07:54 (*)   Elaborating CPU configuration settings 
 
# 2010.10.27 23:07:54 (*)   Creating all objects for CPU 
# 2010.10.27 23:07:54 (*)     Testbench 
# 2010.10.27 23:07:55 (*)     Instruction decoding 
# 2010.10.27 23:07:55 (*)       Instruction fields 
# 2010.10.27 23:07:55 (*)       Instruction decodes 
# 2010.10.27 23:07:56 (*)       Signals for RTL simulation waveforms 
# 2010.10.27 23:07:56 (*)       Instruction controls 
# 2010.10.27 23:07:56 (*)     Pipeline frontend 
# 2010.10.27 23:07:56 (*)     Pipeline backend 
# 2010.10.27 23:08:02 (*)   Generating HDL from CPU objects 
 
# 2010.10.27 23:08:14 (*)   Creating encrypted HDL 
# 2010.10.27 23:08:19 (*)   Creating IP functional simulation model 
 
# 2010.10.27 23:08:58 (*) Running Generator Program for sdram 
 
# 2010.10.27 23:09:09 (*) Running Generator Program for epcs 
 
# 2010.10.27 23:09:12 (*) Running Generator Program for jtag_uart 
 
# 2010.10.27 23:09:14 (*) Running Generator Program for sysid 
 
# 2010.10.27 23:09:16 (*) Running Generator Program for pio_led 
 
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# 2010.10.27 23:09:18 (*) Running Test Generator Program for sdram 
 
# 2010.10.27 23:09:20 (*) Making arbitration and system (top) modules. 
 
# 2010.10.27 23:09:33 (*) Generating Quartus symbol for top level: CPU_LED 
 
# 2010.10.27 23:09:33 (*) Generating Symbol E:/FPGA_System/Altera/NiosII_LED/CPU_LED.bsf 
 
# 2010.10.27 23:09:33 (*) Creating command-line system-generation script: E:/FPGA_System/Altera/NiosII_LED/CPU_LED_generation_script 
 
# 2010.10.27 23:09:33 (*) Running setup for HDL simulator: modelsim 
 
 
Building ModelSim Project 
 
'vsim' 不是内部或外部命令,也不是可运行的程序 
或批处理文件。 
 
# 2010.10.27 23:09:34 (*) Completed generation for system: CPU_LED. 
# 2010.10.27 23:09:34 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED: 
  SOPC Builder database : E:/FPGA_System/Altera/NiosII_LED/CPU_LED.ptf  
  System HDL Model : E:/FPGA_System/Altera/NiosII_LED/CPU_LED.vhd  
  System Generation Script : E:/FPGA_System/Altera/NiosII_LED/CPU_LED_generation_script  
  HDL Simulation Directory : E:/FPGA_System/Altera/NiosII_LED/CPU_LED_sim  
 
# 2010.10.27 23:09:34 (*) SUCCESS: SYSTEM GENERATION COMPLETED. 
 
 
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