www.pudn.com > SRAM_WR.rar > sram_wr.qsf, change:2010-11-05,size:5640b

# -------------------------------------------------------------------------- # 
# Copyright (C) 1991-2009 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files from any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
# -------------------------------------------------------------------------- # 
# Quartus II 
# Version 9.1 Build 222 10/21/2009 SJ Full Version 
# Date created = 15:37:24  November 05, 2010 
# -------------------------------------------------------------------------- # 
# Notes: 
# 1) The default values for assignments are stored in the file: 
#		sram_wr_assignment_defaults.qdf 
#    If this file doesn't exist, see file: 
#		assignment_defaults.qdf 
# 2) Altera recommends that you do not modify this file. This 
#    file is updated automatically by the Quartus II software 
#    and any changes you make may be lost or overwritten. 
# -------------------------------------------------------------------------- # 
set_global_assignment -name FAMILY "Cyclone II" 
set_global_assignment -name DEVICE EP2C35F672C6 
set_global_assignment -name TOP_LEVEL_ENTITY sram_wr 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:37:24  NOVEMBER 05, 2010" 
set_global_assignment -name LAST_QUARTUS_VERSION 9.1 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga 
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 
set_global_assignment -name VERILOG_FILE sram_wr.v 
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 
set_location_assignment PIN_N25 -to iSW[0] 
set_location_assignment PIN_N26 -to iSW[1] 
set_location_assignment PIN_P25 -to iSW[2] 
set_location_assignment PIN_AE14 -to iSW[3] 
set_location_assignment PIN_V2 -to iRW 
set_location_assignment PIN_AE23 -to oledi[0] 
set_location_assignment PIN_AF23 -to oledi[1] 
set_location_assignment PIN_AB21 -to oledi[2] 
set_location_assignment PIN_AC22 -to oledi[3] 
set_location_assignment PIN_AE4 -to oSram_addr[0] 
set_location_assignment PIN_AF4 -to oSram_addr[1] 
set_location_assignment PIN_AC5 -to oSram_addr[2] 
set_location_assignment PIN_AC6 -to oSram_addr[3] 
set_location_assignment PIN_AD4 -to oSram_addr[4] 
set_location_assignment PIN_AD5 -to oSram_addr[5] 
set_location_assignment PIN_AE5 -to oSram_addr[6] 
set_location_assignment PIN_AF5 -to oSram_addr[7] 
set_location_assignment PIN_AD6 -to oSram_addr[8] 
set_location_assignment PIN_AD7 -to oSram_addr[9] 
set_location_assignment PIN_V10 -to oSram_addr[10] 
set_location_assignment PIN_V9 -to oSram_addr[11] 
set_location_assignment PIN_AC7 -to oSram_addr[12] 
set_location_assignment PIN_W8 -to oSram_addr[13] 
set_location_assignment PIN_W10 -to oSram_addr[14] 
set_location_assignment PIN_Y10 -to oSram_addr[15] 
set_location_assignment PIN_AB8 -to oSram_addr[16] 
set_location_assignment PIN_AC8 -to oSram_addr[17] 
set_location_assignment PIN_AD8 -to oSram_dq[0] 
set_location_assignment PIN_AE6 -to oSram_dq[1] 
set_location_assignment PIN_AF6 -to oSram_dq[2] 
set_location_assignment PIN_AA9 -to oSram_dq[3] 
set_location_assignment PIN_AA10 -to oSram_dq[4] 
set_location_assignment PIN_AB10 -to oSram_dq[5] 
set_location_assignment PIN_AA11 -to oSram_dq[6] 
set_location_assignment PIN_Y11 -to oSram_dq[7] 
set_location_assignment PIN_AE7 -to oSram_dq[8] 
set_location_assignment PIN_AF7 -to oSram_dq[9] 
set_location_assignment PIN_AE8 -to oSram_dq[10] 
set_location_assignment PIN_AF8 -to oSram_dq[11] 
set_location_assignment PIN_W11 -to oSram_dq[12] 
set_location_assignment PIN_W12 -to oSram_dq[13] 
set_location_assignment PIN_AC9 -to oSram_dq[14] 
set_location_assignment PIN_AC10 -to oSram_dq[15] 
set_location_assignment PIN_AE10 -to oSram_we_n 
set_location_assignment PIN_AD10 -to oSram_oe_n 
set_location_assignment PIN_AE9 -to oSram_be_n 
set_location_assignment PIN_AC11 -to oSram_ce_n 
set_location_assignment PIN_N2 -to iclk 
set_location_assignment PIN_AF9 -to oSram_be_n[1] 
set_location_assignment PIN_AE9 -to oSram_be_n[0] 
set_global_assignment -name MISC_FILE "D:/FPGA_program/SRAM_WR/sram_wr.dpf" 
set_global_assignment -name USE_CONFIGURATION_DEVICE ON 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 
set_location_assignment PIN_AD22 -to oledo[0] 
set_location_assignment PIN_AD23 -to oledo[1] 
set_location_assignment PIN_AD21 -to oledo[2] 
set_location_assignment PIN_AC21 -to oledo[3] 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top