www.pudn.com > IrDA.rar > uart.c

/*
  Copyright (C) 2002-2003 Gerd Rausch, BlauLogic (http://blaulogic.com)
  All rights reserved.

  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions
  are met:

  1. Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.

  3. Except as contained in this notice, neither the name of BlauLogic
     nor the name(s) of the author(s) may be used to endorse or promote
     products derived from this software without specific prior written
     permission.

  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  IN NO EVENT SHALL THE AUTHOR(S) OR BLAULOGIC BE LIABLE FOR ANY CLAIM,
  DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
  THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

#include 
#include 
#include 

#ifndef AVR_OSC_FREQ
#error please define AVR_OSC_FREQ
#endif

#define AVR_BAUDRATE		9600
#define AVR_UBR_VAL		(AVR_OSC_FREQ/AVR_BAUDRATE/16-1)
#define AVR_DELAY_COUNT		(AVR_OSC_FREQ/6000)

#if defined(UCSR0A)

#define AVR_UBRR_REG		UBRR0
#define AVR_TXEN_REG		UCSR0B
#define AVR_TXEN_BIT		TXEN0
#define AVR_RXEN_REG		UCSR0B
#define AVR_RXEN_BIT		RXEN0
#define AVR_UDRE_REG		UCSR0A
#define AVR_UDRE_BIT		UDRE0
#define AVR_RXC_REG		UCSR0A
#define AVR_RXC_BIT		RXC0
#define AVR_UDR_REG		UDR0

#elif defined(UCSRA)

#ifdef UBRRL
#define AVR_UBRR_REG		UBRRL
#else
#define AVR_UBRR_REG		UBRR
#endif
#define AVR_TXEN_REG		UCSRB
#define AVR_TXEN_BIT		TXEN
#define AVR_RXEN_REG		UCSRB
#define AVR_RXEN_BIT		RXEN
#define AVR_UDRE_REG		UCSRA
#define AVR_UDRE_BIT		UDRE
#define AVR_RXC_REG		UCSRA
#define AVR_RXC_BIT		RXC
#define AVR_UDR_REG		UDR

#else

#define AVR_UBRR_REG		UBRR
#define AVR_TXEN_REG		UCR
#define AVR_TXEN_BIT		TXEN
#define AVR_RXEN_REG		UCR
#define AVR_RXEN_BIT		RXEN
#define AVR_UDRE_REG		USR
#define AVR_UDRE_BIT		UDRE
#define AVR_RXC_REG		USR
#define AVR_RXC_BIT		RXC
#define AVR_UDR_REG		UDR

#endif

#define loop_until_bit_is_set_timeout(port, bit, timeout)					\
  __asm__ __volatile__										\
    ("0:\n"											\
     "  ldi r24, %3\n"										\
     "  ldi r25, %4\n"										\
     "1:\n"											\
     "  sbic %0, %1\n"										\
     "  rjmp 2f\n"										\
     "  sbiw r24, 1\n"										\
     "  brne 1b\n"										\
     "  dec %2\n"										\
     "  brne 0b\n"										\
     "2:\n"											\
     :												\
     : "I" ((uint8_t)((port)-__SFR_OFFSET)), "I" ((uint8_t)(bit)), "r" ((uint8_t)timeout),	\
       "i" ((uint8_t)AVR_DELAY_COUNT), "i" ((uint8_t)(AVR_DELAY_COUNT>>8))			\
     : "r24", "r25")

void irphy_reset(void)
{
  outp(AVR_UBR_VAL, AVR_UBRR_REG);

  sbi(AVR_TXEN_REG, AVR_TXEN_BIT);
  sbi(AVR_RXEN_REG, AVR_RXEN_BIT);
}

void irphy_send(uint8_t v)
{
  loop_until_bit_is_set(AVR_UDRE_REG, AVR_UDRE_BIT);
  outp(v, AVR_UDR_REG);
}

uint8_t irphy_wait(int16_t a_timeout)
{
  int16_t timeout;

  if(a_timeout<0) {
    loop_until_bit_is_set(AVR_RXC_REG, AVR_RXC_BIT);
    return 1;
  }

  for(timeout=a_timeout;
      bit_is_clear(AVR_RXC_REG, AVR_RXC_BIT) && timeout>200;
      timeout-=200)
    loop_until_bit_is_set_timeout(AVR_RXC_REG, AVR_RXC_BIT, 200);

  if(bit_is_clear(AVR_RXC_REG, AVR_RXC_BIT) && timeout>0)
    loop_until_bit_is_set_timeout(AVR_RXC_REG, AVR_RXC_BIT, timeout);

  return bit_is_set(AVR_RXC_REG, AVR_RXC_BIT);
}

uint8_t irphy_receive(void)
{
  loop_until_bit_is_set(AVR_RXC_REG, AVR_RXC_BIT);

  return inp(AVR_UDR_REG);
}