www.pudn.com > XLXH.rar > XLXH.vhd, change:2010-10-28,size:1850b

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
use ieee.std_logic_unsigned.all; 
entity XLXH is  
 port(clk,rst:in std_logic; 
       f,y:out std_logic; 
        c1,c2,c3,c4,c5: buffer std_logic; 
       shuchu:out std_logic_vector(3 downto 0)); 
end XLXH; 
architecture one of XLXH is  
   type state is (s0,s1,s2,s3,s4);---状态机的定义，5个状态 
   signal p:state; 
   signal m,n:std_logic;  
   signal q:std_logic_vector(3 downto 0);--定义信号进行计数 
  begin 
process(clk,rst,q,m)----产生序列的进程 
begin  
    if rst='1' then q<="0000";m<='0';--如果是清零，序列重头产生 
     elsif clk'event and clk='1' then q<=q+1;--时间上升沿产生 
     case q is 
    when "0001" =>m<='1'; 
    when "0010" =>m<='1'; 
    when "0011" =>m<='1'; 
    when "0101" =>m<='1'; 
    when "1000" =>m<='1'; 
    when "1001" =>m<='1'; 
    when "1011" =>m<='1'; 
    when "1100" =>m<='1'; 
    when "1110" =>m<='1'; 
    when others =>m<='0'; 
     end case;   
     end if; 
end process; 
process(rst,clk,p,n)----序列检测器进程 
variable q1:std_logic_vector(3 downto 0):="0000";--变量进行计数 
 begin  
 if rst='1' then 
p<=s0;n<='0';q1:="0000";c5<='0';c4<='0';c3<='0';c2<='0';c1<='0'; 
 elsif clk'event and clk='0'  then n<='0'; 
  case p is 
 when s0 => if m='1' then p<=s1;else p<=s0;end if; 
 when s1 => if m='1' then p<=s2;else p<=s0;end if; 
 when s2 => if m='0' then p<=s3;else p<=s2;end if; 
 when s3 => if m='1' then p<=s4;else p<=s0;end if; 
 when s4 => if m='0' then p<=s0;n<='1'; 
 if q1<10 then q1:=q1+1; 
 else q1:="0000"; 
 end if; 
 else p<=s2;end if;--11011010里有一个，同时计数 
 when others=> p<=s0; 
end case; 
     c5<=c4;---移位输出显示在led上以便观看 
     c4<=c3; 
     c3<=c2; 
     c2<=c1; 
     c1<=m;--将最近生产的序列赋给最前端的c1位 
end if; 
shuchu<=q1; 
y<=n;--显示当前5个位正确 
end process; 
 f<=m;--显示当前生产的位的高低 
end one;