www.pudn.com > EDA3add.rar > SCHK.vhd, change:2009-10-30,size:2760b


LIBRARY IEEE ; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY SCHK IS 
          PORT(CLK :IN STD_LOGIC; 
	            RST:IN STD_LOGIC;  
		        CLR:IN STD_LOGIC;  
		    DATA_IN:IN STD_LOGIC;  
		   DATA_OUT:OUT STD_LOGIC; 
		      COUNT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);      
		        LED: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  
END SCHK; 
ARCHITECTURE behav OF SCHK IS 
    SIGNAL QQ:STD_LOGIC; 
    type states is (S0,S1,S2,S3,S4,S5);  --定义6个状态 
    signal SX:states;                --状态变量 
    SIGNAL D : STD_LOGIC_VECTOR(4 DOWNTO 0); --5位待检测预置数 
 BEGIN 
 
  PROCESS( CLK, CLR )                                --16位移位寄存器 
      VARIABLE REG: STD_LOGIC_VECTOR(15 DOWNTO 0);   
       BEGIN 
           IF CLR='1' THEN  REG:="0000000000000000";  --移位寄存器清零          
           elsIF  CLK'EVENT AND CLK='1' THEN   
             REG(15 DOWNTO 1):= REG(14 DOWNTO 0);   --右移一位 
             REG(0):=DATA_IN;                        --将输入序列寄存到寄存器 
           END IF; 
        LED<=REG(7 DOWNTO 0);                       --LED灯显示 
   END PROCESS; 
    
   D <= "11010"  ; --5位待检测预置数 
  PROCESS( CLK, CLR )                                --序列检测器 
  BEGIN 
  IF CLR = '1' THEN    SX<= S0 ; 
     ELSIF  CLK'EVENT AND CLK='1' THEN  --时钟沿到来时,判断并处理当前输入的位 
     CASE SX IS 
         WHEN S0=>  IF DATA_IN = D(4) THEN SX<= S1 ; ELSE SX<= S0 ; END IF ; 
         WHEN S1=>  IF DATA_IN = D(3) THEN SX<= S2 ; ELSE SX<= S0 ; END IF ; 
         WHEN S2=>  IF DATA_IN = D(2) THEN SX<= S3 ; ELSE SX<= S2 ; END IF ; 
         WHEN S3=>  IF DATA_IN = D(1) THEN SX<= S4 ; ELSE SX<= S0 ; END IF ; 
         WHEN S4=>  IF DATA_IN = D(0) THEN SX<= S5 ; ELSE SX<= S2 ; END IF ; 
         WHEN S5=>  IF DATA_IN = D(4) THEN SX<= S1 ; ELSE SX<= S0 ; END IF ; 
         WHEN OTHERS =>  SX <= S0 ; 
     END CASE ; 
  END IF ; 
  END PROCESS ; 
   
  PROCESS( SX )                        --检测结果判断输出 
  BEGIN 
      IF SX = S5  THEN  QQ <= '1' ;     --序列数检测正确,输出 1 
            ELSE      QQ <= '0' ;     --序列数检测错误,输出 0 
      END IF ; 
   DATA_OUT<=QQ; 
  END PROCESS ; 
   
PROCESS(CLK, RST, QQ)                                --十进制计数器 
   VARIABLE  CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);  
   BEGIN 
      IF RST = '1' THEN   CQI := (OTHERS =>'0') ;          --计数器复位           
      ELSIF QQ'EVENT AND QQ='1' THEN                 --检测时钟上升沿 
          IF CQI < "1001" THEN   CQI := CQI + 1;         --允许计数   
            ELSE    CQI := (OTHERS =>'0');              --大于9,计数值清零        
          END IF; 
      END IF;    
    COUNT <= CQI;                                  --将计数值向端口输出 
   END PROCESS; 
 
END behav ;