www.pudn.com > EDA3add.rar > SCHK.qsf, change:2009-10-30,size:2326b

# -------------------------------------------------------------------------- # 
# 
# Copyright (C) 1991-2009 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files from any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
# 
# -------------------------------------------------------------------------- # 
# 
# Quartus II 
# Version 9.0 Build 132 02/25/2009 SJ Full Version 
# Date created = 11:55:14  October 30, 2009 
# 
# -------------------------------------------------------------------------- # 
# 
# Notes: 
# 
# 1) The default values for assignments are stored in the file: 
#		SCHK_assignment_defaults.qdf 
#    If this file doesn't exist, see file: 
#		assignment_defaults.qdf 
# 
# 2) Altera recommends that you do not modify this file. This 
#    file is updated automatically by the Quartus II software 
#    and any changes you make may be lost or overwritten. 
# 
# -------------------------------------------------------------------------- # 
 
 
set_global_assignment -name FAMILY ACEX1K 
set_global_assignment -name DEVICE "EP1K100QC208-3" 
set_global_assignment -name TOP_LEVEL_ENTITY SCHK 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:55:14  OCTOBER 30, 2009" 
set_global_assignment -name LAST_QUARTUS_VERSION 9.0 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga 
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 
set_global_assignment -name VHDL_FILE SCHK.vhd 
set_global_assignment -name VECTOR_WAVEFORM_FILE SCHK.vwf 
set_global_assignment -name SIMULATION_MODE FUNCTIONAL