www.pudn.com > digital_lock.rar > traffic_light.vhd, change:2009-04-22,size:5004b

--****************************************Copyright (c)************************************************** 
--                               BeiJing Universal Pioneering Technology CO.,LTD. 
--                                      Research Centre 
--                                   http://www.up-tech.com 
-- 
-----------------------------------------File Info------------------------------------------------------- 
-- File name:			traffic_light.vhd 
-- Last modified Date:	2009-04-08 
-- Last Version:		1.0 
-- Descriptions:		simulate the traffic light 
--                                                      green yellow red 
--											      red                     green 
--												  yellow                  yellow 
--												  green					  red 
--														red   yellow green 
-- 
--------------------------------------------------------------------------------------------------------- 
-- Created by:			Peng Kailai 
-- Created date:		2009-04-08 
-- Version:				1.0 
-- Descriptions:		The original version 
-- 
--------------------------------------------------------------------------------------------------------- 
-- Modified by:			 
-- Modified date:		 
-- Version:				 
-- Descriptions:		 
-- 
--------------------------------------------------------------------------------------------------------- 
--******************************************************************************************************** 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity traffic_light is 
port 
( 
	clk,rst,en: in  std_logic; 
    seven_seg : out std_logic_vector(15 downto 0); 
    lamp      : out std_logic_vector(5 downto 0) 
); 
end traffic_light; 
 
architecture rt1 of traffic_light is 
signal num                   :std_logic_vector(7 downto 0); 
signal temp                  :std_logic; 
signal Y_r_1,Y_r_2           :std_logic_vector(7 downto 0); 
type st is(red,yellow1,green,yellow2); 
signal current_state: st; 
 
 
begin 
	process(clk,rst,en) 
	begin 
		if(clk'event and clk = '1')then 
			if rst = '0' then 
				current_state <= red; 
				temp <= '0'; 
				lamp <= "111111"; 
			else 
				if en = '1' then 
					if temp = '0' then 
					   temp <= '1'; 
					   case (current_state) is 
							when red=> 
									num <= "00100101";  --25 
									lamp <= "011110";  
									current_state <= green; 
							when green=> 
									num <= "00100000"; --20 
									lamp <= "110011"; 
									current_state <= yellow1; 
							when yellow1=> 
									num <= "00000101";  --5 
									lamp <= "101101"; 
									current_state <= red; 
							when others=>	 
									lamp <= "011110"; 
					   end case; 
					else 
						if num > "00000001" then 
							if num(3 downto 0) = "0000" then 
								num(3 downto 0) <= "1001"; 
								num(7 downto 4) <= num(7 downto 4) - 1; 
							else 
								num(3 downto 0) <= num(3 downto 0) - 1; 
							end if; 
							if num = "00000010" then 
								temp <= '0'; 
							end if; 
						end if; 
					end if; 
				else 
					lamp <= "111111"; 
					current_state <= red; 
					temp <= '0'; 
				end if; 
			end if; 
	    end if; 
	end process;    
	 
	 
	seven_seg(15 downto 8) <= Y_r_1; 
	seven_seg(7 downto 0) <= Y_r_2; 
	 
	process(num(3 downto 0)) 
	begin 
		Y_r_1 <= "11111111"; 
		case (num(3 downto 0)) is 
			 when "0000" => Y_r_1 <="11000000"; --0 
			 when "0001" => Y_r_1 <="11111001"; --1 
			 when "0010" => Y_r_1 <="10100100"; --2 
			 when "0011" => Y_r_1 <="10110000"; --3 
			 when "0100" => Y_r_1 <="10011001"; --4 
			 when "0101" => Y_r_1 <="10010010"; --5 
			 when "0110" => Y_r_1 <="10000010"; --6 
			 when "0111" => Y_r_1 <="11111000"; --7 
			 when "1000" => Y_r_1 <="10000000"; --8 
			 when "1001" => Y_r_1 <="10010000"; --9 
			 when "1010" => Y_r_1 <="10001000"; --a 
			 when "1011" => Y_r_1 <="10000011"; --b 
			 when "1100" => Y_r_1 <="11000110"; --c 
			 when "1101" => Y_r_1 <="10100001"; --d 
			 when "1110" => Y_r_1 <="10000110"; --e 
			 when "1111" => Y_r_1 <="10001110"; --f 
			 when others => Y_r_1 <="10000000"; 
		end case; 
	end process; 
	 
	process(num(7 downto 4)) 
	begin 
		Y_r_2 <= "11111111"; 
		case (num(7 downto 4)) is 
			 when "0000" => Y_r_2 <="11000000"; --0 
			 when "0001" => Y_r_2 <="11111001"; --1 
			 when "0010" => Y_r_2 <="10100100"; --2 
			 when "0011" => Y_r_2 <="10110000"; --3 
			 when "0100" => Y_r_2 <="10011001"; --4 
			 when "0101" => Y_r_2 <="10010010"; --5 
			 when "0110" => Y_r_2 <="10000010"; --6 
			 when "0111" => Y_r_2 <="11111000"; --7 
			 when "1000" => Y_r_2 <="10000000"; --8 
			 when "1001" => Y_r_2 <="10010000"; --9 
			 when "1010" => Y_r_2 <="10001000"; --a 
			 when "1011" => Y_r_2 <="10000011"; --b 
			 when "1100" => Y_r_2 <="11000110"; --c 
			 when "1101" => Y_r_2 <="10100001"; --d 
			 when "1110" => Y_r_2 <="10000110"; --e 
			 when "1111" => Y_r_2 <="10001110"; --f 
			 when others => Y_r_2 <="10000000"; 
		end case; 
	end process; 
end rt1;