www.pudn.com > digital_lock.rar > frediv.vhd, change:2009-04-21,size:2202b


--****************************************Copyright (c)************************************************** 
--                               BeiJing Universal Pioneering Technology CO.,LTD. 
--                                      Research Centre 
--                                   http://www.up-tech.com 
-- 
-----------------------------------------File Info------------------------------------------------------- 
-- File name:			frediv.vhd 
-- Last modified Date:	2009-04-08 
-- Last Version:		1.0 
-- Descriptions:		generate the required frequency to disp and traffic light 
-- 
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-- Created by:			Peng Kailai 
-- Created date:		2009-04-08 
-- Version:				1.0 
-- Descriptions:		The original version 
-- 
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-- Modified by:			 
-- Modified date:		 
-- Version:				 
-- Descriptions:		 
-- 
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--******************************************************************************************************** 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity frediv is 
port 
( 
	clk		   : in  std_logic; 
	clk_disp   : out std_logic; 
	clk_traffic: out std_logic 
); 
end frediv; 
 
architecture rt1 of frediv is 
begin 
	process(clk) 
	variable count1:integer range 0 to 50000000; 
	begin 
		if clk'event and clk = '1' then 
			if count1 = 49999999 then 
				count1 := 0; 
			else 
				count1 := count1 + 1; 
				if count1 <= 24999999 then 
					clk_traffic <= '0' ; 
				else 
					clk_traffic <= '1' ; 
				end if; 
			end if; 
		end if; 
     end process; 
      
     process(clk) 
	variable count2:integer range 0 to 50000000; 
	 begin 
		if clk'event and clk = '1' then 
			if count2 = 249999 then 
				count2 := 0; 
			else 
				count2 := count2 + 1; 
				if count2 <= 124999 then 
					clk_disp <= '0' ; 
				else 
					clk_disp <= '1' ; 
				end if; 
			end if; 
		end if; 
	end process; 
end rt1;