www.pudn.com > digital_lock.rar > disp.vhd, change:2009-04-21,size:4072b


--****************************************Copyright (c)************************************************** 
--                               BeiJing Universal Pioneering Technology CO.,LTD. 
--                                      Research Centre 
--                                   http://www.up-tech.com 
-- 
-----------------------------------------File Info------------------------------------------------------- 
-- File name:			disp.vhd 
-- Last modified Date:	2009-04-08 
-- Last Version:		1.0 
-- Descriptions:		use the two static segment to display the left time 
-- 
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-- Created by:			Peng Kailai 
-- Created date:		2009-04-08 
-- Version:				1.0 
-- Descriptions:		The original version 
-- 
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-- Modified by:			 
-- Modified date:		 
-- Version:				 
-- Descriptions:		 
-- 
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--******************************************************************************************************** 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity disp is 
port 
( 
	clk,rst      : in  std_logic;	 
	seven_seg    : in  std_logic_vector(15 downto 0); 
	shcp,slcp    : out std_logic; 
    data_out     : out std_logic 
); 
end disp; 
 
architecture rt1 of disp is 
signal slcp_r,data_out_r:std_logic; 
 
type st is(start,bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8,bit9,bit10,bit11,bit12,bit13,bit14,bit15,push,idle); 
signal p_state,n_state:st; 
begin 
	data_out <= data_out_r; 
	slcp <= slcp_r; 
	shcp <= clk; 
	process(clk,rst,seven_seg,p_state) 
	begin 
		if clk'event and clk = '1'then 
			if rst = '0' then 
				p_state <= idle; 
			else 
				case (p_state) is 
					when idle => slcp_r <= '1'; p_state <= bit0; 
					when bit0 =>  
								data_out_r <= seven_seg(15);  
								slcp_r <= '0';  
								p_state <= bit1; 
					when bit1 =>  
								data_out_r <= seven_seg(14);  
								slcp_r <= '0';  
								p_state <= bit2; 
					when bit2 =>  
								data_out_r <= seven_seg(13);  
								slcp_r <= '0';  
								p_state <= bit3; 
					when bit3 => 
								data_out_r <= seven_seg(12);  
								slcp_r <= '0';  
								p_state <= bit4; 
					when bit4 =>  
								data_out_r <= seven_seg(11);  
								slcp_r <= '0';  
								p_state <= bit5; 
					when bit5 =>  
								data_out_r <= seven_seg(10);  
								slcp_r <= '0';  
								p_state <= bit6; 
					when bit6 =>  
								data_out_r <= seven_seg(9);  
								slcp_r <= '0';  
								p_state <= bit7; 
					when bit7 =>  
								data_out_r <= seven_seg(8);  
								slcp_r <= '0';  
								p_state <= bit8; 
					when bit8 =>  
								data_out_r <= seven_seg(7);  
								slcp_r <= '0';  
								p_state <= bit9; 
					when bit9 =>  
								data_out_r <= seven_seg(6);  
								slcp_r <= '0';  
								p_state <= bit10; 
					when bit10 =>  
								data_out_r <= seven_seg(5);  
								slcp_r <= '0';  
								p_state <= bit11; 
					when bit11 =>  
								data_out_r <= seven_seg(4);  
								slcp_r <= '0';  
								p_state <= bit12; 
					when bit12 =>  
								data_out_r <= seven_seg(3);  
								slcp_r <= '0';  
								p_state <= bit13; 
					when bit13 =>  
								data_out_r <= seven_seg(2);  
								slcp_r <= '0';  
								p_state <= bit14; 
					when bit14 =>  
								data_out_r <= seven_seg(1);  
								slcp_r <= '0';  
								p_state <= bit15; 
					when bit15 =>  
								data_out_r <= seven_seg(0);  
								slcp_r <= '0';  
								p_state <= start; 
					when start =>  
								data_out_r <= '0';  
								slcp_r <= '0';  
								p_state <= push; 
					when push =>  
								data_out_r <= '1';  
								slcp_r <= '1';  
								p_state <= idle; 
					when others=> 
								p_state <= idle; 
				end case; 
			end if; 
		end if; 
	end process; 
end rt1;