www.pudn.com > x86.rar > shrd.v, change:2007-12-05,size:3541b


module shrd(shiftout,shiftedoutbit,shiftin1,shiftin2,count); 
input [31:0] shiftin1; 
input [31:0] shiftin2; 
input [4:0] count; 
output [31:0] shiftout; 
output shiftedoutbit; 
reg [31:0] shiftout; 
reg shiftedoutbit; 
always @(shiftin1 or shiftin2 or count) 
 begin 
   case(count) 
      5'd0: begin shiftout = shiftin1; shiftedoutbit = 1'b0; end 
      5'd1: begin shiftout = {shiftin2[0],shiftin1[31:1]};      shiftedoutbit = shiftin1[0];  end 
      5'd2: begin  shiftout = {shiftin2[1:0],shiftin1[31:2]};   shiftedoutbit = shiftin1[1];  end 
      5'd3: begin  shiftout = {shiftin2[2:0],shiftin1[31:3]};   shiftedoutbit = shiftin1[2];  end 
      5'd4: begin  shiftout = {shiftin2[3:0],shiftin1[31:4]};   shiftedoutbit = shiftin1[3];  end 
      5'd5: begin  shiftout = {shiftin2[4:0],shiftin1[31:5]};   shiftedoutbit = shiftin1[4];  end 
      5'd6: begin  shiftout = {shiftin2[5:0],shiftin1[31:6]};   shiftedoutbit = shiftin1[5];  end 
      5'd7: begin  shiftout = {shiftin2[6:0],shiftin1[31:7]};   shiftedoutbit = shiftin1[6];  end 
      5'd8: begin  shiftout = {shiftin2[7:0],shiftin1[31:8]};   shiftedoutbit = shiftin1[7];  end 
      5'd9: begin  shiftout = {shiftin2[8:0],shiftin1[31:9]};   shiftedoutbit = shiftin1[8];  end 
      5'd10: begin  shiftout = {shiftin2[9:0],shiftin1[31:10]};   shiftedoutbit = shiftin1[9];  end 
      5'd11: begin  shiftout = {shiftin2[10:0],shiftin1[31:11]};   shiftedoutbit = shiftin1[10];  end 
      5'd12: begin  shiftout = {shiftin2[11:0],shiftin1[31:12]};   shiftedoutbit = shiftin1[11];  end 
      5'd13: begin  shiftout = {shiftin2[12:0],shiftin1[31:13]};   shiftedoutbit = shiftin1[12];  end 
      5'd14: begin  shiftout = {shiftin2[13:0],shiftin1[31:14]};   shiftedoutbit = shiftin1[13];  end 
      5'd15: begin  shiftout = {shiftin2[14:0],shiftin1[31:15]};   shiftedoutbit = shiftin1[14];  end 
      5'd16: begin  shiftout = {shiftin2[15:0],shiftin1[31:16]};   shiftedoutbit = shiftin1[15];  end 
      5'd17: begin  shiftout = {shiftin2[16:0],shiftin1[31:17]};   shiftedoutbit = shiftin1[16];  end 
      5'd18: begin  shiftout = {shiftin2[17:0],shiftin1[31:18]};   shiftedoutbit = shiftin1[17];  end 
      5'd19: begin  shiftout = {shiftin2[18:0],shiftin1[31:19]};   shiftedoutbit = shiftin1[18];  end 
      5'd20: begin  shiftout = {shiftin2[19:0],shiftin1[31:20]};   shiftedoutbit = shiftin1[19];  end 
      5'd21: begin  shiftout = {shiftin2[20:0],shiftin1[31:21]};   shiftedoutbit = shiftin1[20];  end 
      5'd22: begin  shiftout = {shiftin2[21:0],shiftin1[31:22]};   shiftedoutbit = shiftin1[21];  end 
      5'd23: begin  shiftout = {shiftin2[22:0],shiftin1[31:23]};   shiftedoutbit = shiftin1[22];  end 
      5'd24: begin  shiftout = {shiftin2[23:0],shiftin1[31:24]};   shiftedoutbit = shiftin1[23];  end 
      5'd25: begin  shiftout = {shiftin2[24:0],shiftin1[31:25]};   shiftedoutbit = shiftin1[24];  end 
      5'd26: begin  shiftout = {shiftin2[25:0],shiftin1[31:26]};   shiftedoutbit = shiftin1[25];  end 
      5'd27: begin  shiftout = {shiftin2[26:0],shiftin1[31:27]};   shiftedoutbit = shiftin1[26];  end 
      5'd28: begin  shiftout = {shiftin2[27:0],shiftin1[31:28]};   shiftedoutbit = shiftin1[27];  end 
      5'd29: begin  shiftout = {shiftin2[28:0],shiftin1[31:29]};   shiftedoutbit = shiftin1[28];  end 
      5'd30: begin  shiftout = {shiftin2[29:0],shiftin1[31:30]};   shiftedoutbit = shiftin1[29];  end 
      5'd31: begin  shiftout = {shiftin2[30:0],shiftin1[31]};   shiftedoutbit = shiftin1[30];  end 
   endcase 
 end 
endmodule