www.pudn.com > x86.rar > shld.v, change:2007-12-05,size:3549b


module shld(shiftout,shiftedoutbit,shiftin1,shiftin2,count); 
input [31:0] shiftin1; 
input [31:0] shiftin2; 
input [4:0] count; 
output [31:0] shiftout; 
output shiftedoutbit; 
reg [31:0] shiftout; 
reg shiftedoutbit; 
always @(shiftin1 or shiftin2 or count) 
 begin 
   case(count) 
      5'd0: begin shiftout = shiftin1; shiftedoutbit = 1'b0; end 
      5'd01: begin  shiftout = {shiftin1[30:0],shiftin2[31:31]};  shiftedoutbit = shiftin1[31];  end 
      5'd02: begin  shiftout = {shiftin1[29:0],shiftin2[31:30]};  shiftedoutbit = shiftin1[30];  end 
      5'd03: begin  shiftout = {shiftin1[28:0],shiftin2[31:29]};  shiftedoutbit = shiftin1[29];  end 
      5'd04: begin  shiftout = {shiftin1[27:0],shiftin2[31:28]};  shiftedoutbit = shiftin1[28];  end 
      5'd05: begin  shiftout = {shiftin1[26:0],shiftin2[31:27]};  shiftedoutbit = shiftin1[27];  end 
      5'd06: begin  shiftout = {shiftin1[25:0],shiftin2[31:26]};  shiftedoutbit = shiftin1[26];  end 
      5'd07: begin  shiftout = {shiftin1[24:0],shiftin2[31:25]};  shiftedoutbit = shiftin1[25];  end 
      5'd08: begin  shiftout = {shiftin1[23:0],shiftin2[31:24]};  shiftedoutbit = shiftin1[24];  end 
      5'd09: begin  shiftout = {shiftin1[22:0],shiftin2[31:23]};  shiftedoutbit = shiftin1[23];  end 
      5'd10: begin  shiftout = {shiftin1[21:0],shiftin2[31:22]};  shiftedoutbit = shiftin1[22];  end 
      5'd11: begin  shiftout = {shiftin1[20:0],shiftin2[31:21]};  shiftedoutbit = shiftin1[21];  end 
      5'd12: begin  shiftout = {shiftin1[19:0],shiftin2[31:20]};  shiftedoutbit = shiftin1[20];  end 
      5'd13: begin  shiftout = {shiftin1[18:0],shiftin2[31:19]};  shiftedoutbit = shiftin1[19];  end 
      5'd14: begin  shiftout = {shiftin1[17:0],shiftin2[31:18]};  shiftedoutbit = shiftin1[18];  end 
      5'd15: begin  shiftout = {shiftin1[16:0],shiftin2[31:17]};  shiftedoutbit = shiftin1[17];  end 
      5'd16: begin  shiftout = {shiftin1[15:0],shiftin2[31:16]};  shiftedoutbit = shiftin1[16];  end 
      5'd17: begin  shiftout = {shiftin1[14:0],shiftin2[31:15]};  shiftedoutbit = shiftin1[15];  end 
      5'd18: begin  shiftout = {shiftin1[13:0],shiftin2[31:14]};  shiftedoutbit = shiftin1[14];  end 
      5'd19: begin  shiftout = {shiftin1[12:0],shiftin2[31:13]};  shiftedoutbit = shiftin1[13];  end 
      5'd20: begin  shiftout = {shiftin1[11:0],shiftin2[31:12]};  shiftedoutbit = shiftin1[12];  end 
      5'd21: begin  shiftout = {shiftin1[10:0],shiftin2[31:11]};  shiftedoutbit = shiftin1[11];  end 
      5'd22: begin  shiftout = {shiftin1[09:0],shiftin2[31:10]};  shiftedoutbit = shiftin1[10];  end 
      5'd23: begin  shiftout = {shiftin1[08:0],shiftin2[31:09]};  shiftedoutbit = shiftin1[09];  end 
      5'd24: begin  shiftout = {shiftin1[07:0],shiftin2[31:08]};  shiftedoutbit = shiftin1[08];  end 
      5'd25: begin  shiftout = {shiftin1[06:0],shiftin2[31:07]};  shiftedoutbit = shiftin1[07];  end 
      5'd26: begin  shiftout = {shiftin1[05:0],shiftin2[31:06]};  shiftedoutbit = shiftin1[06];  end 
      5'd27: begin  shiftout = {shiftin1[04:0],shiftin2[31:05]};  shiftedoutbit = shiftin1[05];  end 
      5'd28: begin  shiftout = {shiftin1[03:0],shiftin2[31:04]};  shiftedoutbit = shiftin1[04];  end 
      5'd29: begin  shiftout = {shiftin1[02:0],shiftin2[31:03]};  shiftedoutbit = shiftin1[03];  end 
      5'd30: begin  shiftout = {shiftin1[01:0],shiftin2[31:02]};  shiftedoutbit = shiftin1[02];  end 
      5'd31: begin  shiftout = {shiftin1[00:0],shiftin2[31:01]};  shiftedoutbit = shiftin1[01];  end 
   endcase 
 end 
endmodule