www.pudn.com > x86.rar > shift_16_Logical.v, change:2007-12-05,size:2723b


module shift_16_Logical(shiftOut, shiftIn, Count, direction); 
 
input [15:0] shiftIn; 
input [63:0] Count; 
input direction;//  shiftBitIn; 
 
output [15:0]shiftOut; 
 
reg [15:0] shiftOut; 
 
 
always@(shiftIn or Count or direction) 
 begin 
  
 
  case(Count) 
   64'd1: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[14:0], 1'b0}; 
      1: shiftOut = {1'b0, shiftIn[15:1]}; 
     endcase 
    end 
 
   64'd2: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[13:0], 2'd0}; 
      1: shiftOut = {2'b0, shiftIn[15:2]}; 
     endcase 
    end 
 
   64'd3: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[12:0], 3'd0}; 
      1: shiftOut = {3'b0, shiftIn[15:3]}; 
     endcase 
    end 
 
   64'd4: 
    begin 
      case(direction) 
      0: shiftOut = {shiftIn[11:0], 4'b0000}; 
      1: shiftOut = {4'b0, shiftIn[15:4]}; 
     endcase 
    end 
 
   64'd5: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[10:0], 5'd0}; 
      1: shiftOut = {5'd0, shiftIn[15:5]}; 
     endcase 
    end 
 
   64'd6: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[9:0], 6'd0}; 
      1: shiftOut = {6'd0, shiftIn[15:6]}; 
     endcase 
    end 
 
 
   64'd7: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[8:0], 7'd0}; 
      1: shiftOut = {7'd0, shiftIn[15:7]}; 
     endcase 
    end 
 
   64'd8: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[7:0], 8'd0}; 
      1: shiftOut = {8'd0, shiftIn[15:8]}; 
     endcase 
    end 
 
 
 
   64'd9: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[6:0], 9'd0}; 
      1: shiftOut = {9'd0, shiftIn[15:9]}; 
     endcase 
    end 
 
   64'd10: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[5:0], 10'd0}; 
      1: shiftOut = {10'd0, shiftIn[15:10]}; 
     endcase 
    end 
 
 
   64'd11: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[4:0], 11'd0}; 
      1: shiftOut = {11'd0, shiftIn[15:11]}; 
     endcase 
    end 
 
   64'd12: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[3:0], 12'd0}; 
      1: shiftOut = {12'd0, shiftIn[15:12]}; 
     endcase 
    end 
 
 
   64'd13: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[2:0], 13'd0}; 
      1: shiftOut = {13'd0, shiftIn[15:13]}; 
     endcase 
    end 
 
   64'd14: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[1:0], 14'd0}; 
      1: shiftOut = {14'd0, shiftIn[15:14]}; 
     endcase 
    end 
 
   64'd15: 
    begin 
     case(direction) 
      0: shiftOut = {shiftIn[0], 15'd0}; 
      1: shiftOut = {15'd0, shiftIn[15]}; 
     endcase 
    end 
 
 
 
 
   default: 
        shiftOut = 16'd0; 
  endcase 
 
end 
 
 
endmodule