www.pudn.com > x86.rar > shiftArith.v, change:2007-12-05,size:4457b


module shiftArith(shiftOut, shiftBitOut, shiftBitIn, shiftIn, count); 
input [31:0] shiftIn; 
input [4:0] count; 
input shiftBitIn; 
output [31:0] shiftOut; 
output shiftBitOut; 
reg [31:0] shiftOut; 
reg shiftBitOut; 
 
always@(shiftIn or count or shiftBitIn) 
 begin 
  case(count) 
   5'd1: 
    begin 
     shiftBitOut = shiftIn[0]; 
     shiftOut = {shiftIn[31], shiftIn[31:1]}; 
    end 
 
   5'd2: 
    begin 
     shiftBitOut = shiftIn[1]; 
     shiftOut = {{2{shiftIn[31]}}, shiftIn[31:2]}; 
    end 
  
   5'd3: 
    begin 
     shiftBitOut = shiftIn[2]; 
     shiftOut = {{3{shiftIn[31]}}, shiftIn[31:3]}; 
    end 
 
   5'd4: 
    begin 
     shiftBitOut = shiftIn[3]; 
     shiftOut = {{4{shiftIn[31]}}, shiftIn[31:4]}; 
    end 
 
   5'd5: 
    begin 
     shiftBitOut = shiftIn[4]; 
     shiftOut = {{5{shiftIn[31]}}, shiftIn[31:5]}; 
    end 
 
   5'd6: 
    begin 
     shiftBitOut = shiftIn[5]; 
     shiftOut = {{6{shiftIn[31]}}, shiftIn[31:6]}; 
    end 
 
   5'd7: 
    begin 
     shiftBitOut = shiftIn[6]; 
     shiftOut = {{7{shiftIn[31]}}, shiftIn[31:7]}; 
    end 
 
   5'd8: 
    begin 
     shiftBitOut = shiftIn[7]; 
     shiftOut = {{8{shiftIn[31]}}, shiftIn[31:8]}; 
    end 
 
   5'd9: 
    begin 
     shiftBitOut = shiftIn[8]; 
     shiftOut = {{9{shiftIn[31]}}, shiftIn[31:9]}; 
    end 
 
   5'd10: 
    begin 
     shiftBitOut = shiftIn[9]; 
     shiftOut = {{10{shiftIn[31]}}, shiftIn[31:10]}; 
    end 
 
   5'd11: 
    begin 
     shiftBitOut = shiftIn[10]; 
     shiftOut = {{11{shiftIn[31]}}, shiftIn[31:11]}; 
    end 
 
   5'd12: 
    begin 
     shiftBitOut = shiftIn[11]; 
     shiftOut = {{12{shiftIn[31]}}, shiftIn[31:12]}; 
    end 
 
   5'd13: 
    begin 
     shiftBitOut = shiftIn[12]; 
     shiftOut = {{13{shiftIn[31]}}, shiftIn[31:13]}; 
    end 
 
   5'd14: 
    begin 
     shiftBitOut = shiftIn[13]; 
     shiftOut = {{14{shiftIn[31]}}, shiftIn[31:14]}; 
    end 
 
   5'd15: 
    begin 
     shiftBitOut = shiftIn[14]; 
     shiftOut = {{15{shiftIn[31]}}, shiftIn[31:15]}; 
    end 
 
   5'd16: 
    begin 
     shiftBitOut = shiftIn[15]; 
     shiftOut = {{16{shiftIn[31]}}, shiftIn[31:16]}; 
    end 
 
   5'd17: 
    begin 
     shiftBitOut = shiftIn[16]; 
     shiftOut = {{17{shiftIn[31]}}, shiftIn[31:17]}; 
    end 
 
   5'd18: 
    begin 
     shiftBitOut = shiftIn[17]; 
     shiftOut = {{18{shiftIn[31]}}, shiftIn[31:18]}; 
    end 
 
   5'd19: 
    begin 
     shiftBitOut = shiftIn[18]; 
     shiftOut = {{19{shiftIn[31]}}, shiftIn[31:19]}; 
    end 
 
   5'd20: 
    begin 
     shiftBitOut = shiftIn[19]; 
     shiftOut = {{20{shiftIn[31]}}, shiftIn[31:20]}; 
    end 
 
   5'd21: 
    begin 
     shiftBitOut = shiftIn[20]; 
     shiftOut = {{21{shiftIn[31]}}, shiftIn[31:21]}; 
    end 
 
   5'd22: 
    begin 
     shiftBitOut = shiftIn[21]; 
     shiftOut = {{22{shiftIn[31]}}, shiftIn[31:22]}; 
    end 
 
   5'd23: 
    begin 
     shiftBitOut = shiftIn[22]; 
     shiftOut = {{23{shiftIn[31]}}, shiftIn[31:23]}; 
    end 
 
   5'd24: 
    begin 
     shiftBitOut = shiftIn[23]; 
     shiftOut = {{24{shiftIn[31]}}, shiftIn[31:24]}; 
    end 
 
   5'd25: 
    begin 
     shiftBitOut = shiftIn[24]; 
     shiftOut = {{25{shiftIn[31]}}, shiftIn[31:25]}; 
    end 
 
   5'd26: 
    begin 
     shiftBitOut = shiftIn[25]; 
     shiftOut = {{26{shiftIn[31]}}, shiftIn[31:26]}; 
    end 
 
   5'd27: 
    begin 
     shiftBitOut = shiftIn[26]; 
     shiftOut = {{27{shiftIn[31]}}, shiftIn[31:27]}; 
    end 
 
   5'd28: 
    begin 
     shiftBitOut = shiftIn[27]; 
     shiftOut = {{28{shiftIn[31]}}, shiftIn[31:28]}; 
    end 
 
   5'd29: 
    begin 
     shiftBitOut = shiftIn[28]; 
     shiftOut = {{29{shiftIn[31]}}, shiftIn[31:29]}; 
    end 
 
   5'd30: 
    begin 
     shiftBitOut = shiftIn[29]; 
     shiftOut = {{30{shiftIn[31]}}, shiftIn[31:30]}; 
    end 
 
   5'd31: 
    begin 
     shiftBitOut = shiftIn[30]; 
     shiftOut = {{31{shiftIn[31]}}, shiftIn[31]}; 
    end 
   default: 
     begin 
       shiftBitOut = shiftBitIn; 
       shiftOut = shiftIn;  
     end 
  endcase 
 
 end 
endmodule 
 
/* 
module shiftTest; 
wire [31:0] shiftOut; 
wire shiftBitOut; 
reg [31:0] shiftIn; 
reg [4:0] count; 
reg shiftbitin; 
shiftArith shiftInst(shiftOut, shiftBitOut,shiftbitin, shiftIn, count); 
initial 
 begin 
  shiftbitin=0; 
  shiftIn = 32'h8000_0000; 
  count = 2; 
 end 
 
initial 
 $monitor("shiftIn = %h, shiftOut = %h\n", shiftIn, shiftOut); 
endmodule 
 
*/