www.pudn.com > x86.rar > shift32Arith.v, change:2007-12-05,size:3017b


module shift32Arith(shiftOut, shiftIn, count); 
input [31:0] shiftIn; 
input [63:0] count; 
output [31:0] shiftOut; 
reg [31:0] shiftOut; 
 
always@(shiftIn or count) 
 begin 
  case(count) 
   6'd1: 
    begin 
     shiftOut = {shiftIn[31], shiftIn[31:1]}; 
    end 
 
   6'd2: 
    begin 
     shiftOut = {{2{shiftIn[31]}}, shiftIn[31:2]}; 
    end 
 
   6'd3: 
    begin 
     shiftOut = {{3{shiftIn[31]}}, shiftIn[31:3]}; 
    end 
 
   6'd4: 
    begin 
     shiftOut = {{4{shiftIn[31]}}, shiftIn[31:4]}; 
    end 
 
   6'd5: 
    begin 
     shiftOut = {{5{shiftIn[31]}}, shiftIn[31:5]}; 
    end 
 
   6'd6: 
    begin 
     shiftOut = {{6{shiftIn[31]}}, shiftIn[31:6]}; 
    end 
 
   6'd7: 
    begin 
     shiftOut = {{7{shiftIn[31]}}, shiftIn[31:7]}; 
    end 
 
   6'd8: 
    begin 
     shiftOut = {{8{shiftIn[31]}}, shiftIn[31:8]}; 
    end 
 
   6'd9: 
    begin 
     shiftOut = {{9{shiftIn[31]}}, shiftIn[31:9]}; 
    end 
 
   6'd10: 
    begin 
     shiftOut = {{10{shiftIn[31]}}, shiftIn[31:10]}; 
    end 
 
   6'd11: 
    begin 
     shiftOut = {{11{shiftIn[31]}}, shiftIn[31:11]}; 
    end 
 
   6'd12: 
    begin 
     shiftOut = {{12{shiftIn[31]}}, shiftIn[31:12]}; 
    end 
 
   6'd13: 
    begin 
     shiftOut = {{13{shiftIn[31]}}, shiftIn[31:13]}; 
    end 
 
   6'd14: 
    begin 
     shiftOut = {{14{shiftIn[31]}}, shiftIn[31:14]}; 
    end 
 
   6'd15: 
    begin 
     shiftOut = {{15{shiftIn[31]}}, shiftIn[31:15]}; 
    end 
 
   6'd16: 
    begin 
     shiftOut = {{16{shiftIn[31]}}, shiftIn[31:16]}; 
    end 
 
   6'd17: 
    begin 
     shiftOut = {{17{shiftIn[31]}}, shiftIn[31:17]}; 
    end 
 
   6'd18: 
    begin 
     shiftOut = {{18{shiftIn[31]}}, shiftIn[31:18]}; 
    end 
 
   6'd19: 
    begin 
     shiftOut = {{19{shiftIn[31]}}, shiftIn[31:19]}; 
    end 
 
   6'd20: 
    begin 
     shiftOut = {{20{shiftIn[31]}}, shiftIn[31:20]}; 
    end 
 
   6'd21: 
    begin 
     shiftOut = {{21{shiftIn[31]}}, shiftIn[31:21]}; 
    end 
 
   6'd22: 
    begin 
     shiftOut = {{22{shiftIn[31]}}, shiftIn[31:22]}; 
    end 
 
   6'd23: 
    begin 
     shiftOut = {{23{shiftIn[31]}}, shiftIn[31:23]}; 
    end 
 
   6'd24: 
    begin 
     shiftOut = {{24{shiftIn[31]}}, shiftIn[31:24]}; 
    end 
 
   6'd25: 
    begin 
     shiftOut = {{25{shiftIn[31]}}, shiftIn[31:25]}; 
    end 
 
   6'd26: 
    begin 
     shiftOut = {{26{shiftIn[31]}}, shiftIn[31:26]}; 
    end 
 
   6'd27: 
    begin 
     shiftOut = {{27{shiftIn[31]}}, shiftIn[31:27]}; 
    end 
 
   6'd28: 
    begin 
     shiftOut = {{28{shiftIn[31]}}, shiftIn[31:28]}; 
    end 
 
   6'd29: 
    begin 
     shiftOut = {{29{shiftIn[31]}}, shiftIn[31:29]}; 
    end 
 
   6'd30: 
    begin 
     shiftOut = {{30{shiftIn[31]}}, shiftIn[31:30]}; 
    end 
 
   6'd31: 
    begin 
     shiftOut = {{31{shiftIn[31]}}, shiftIn[31]}; 
    end 
 
   6'd32: 
    begin 
     shiftOut = {32{shiftIn[31]}}; 
    end 
 
 
   default: 
     begin 
       shiftOut = shiftIn; 
     end 
  endcase 
 
 end 
endmodule