www.pudn.com > x86.rar > multiply32.v, change:2007-12-05,size:13221b


module multiply32( product, operand1, operand2,sign);


output [63:0] product;
input [31:0] operand1,operand2;

input sign;

wire [31:0] p0,p1,p2,p3;

wire [31:0] a;
wire [31:0] b,tcOperand1,tcOperand2;
wire [63:0] tProduct,tcProduct;




twosComp multwoscomp1(tcOperand1,operand1);
twosComp multwoscomp2(tcOperand2,operand2);

assign b=sign?(operand2[31]? tcOperand2 : operand2) : operand2;
assign a=sign?(operand1[31]? tcOperand1 : operand1) : operand1;



multiply16 m1(p0[31:0],a[15:0], b[15:0] );
multiply16 m2(p1[31:0],a[15:0], b[31:16]);
multiply16 m3(p2[31:0],a[31:16],b[15:0] );
multiply16 m4(p3[31:0],a[31:16],b[31:16]);

// carrysave adder 1

wire [47:0] sum1;
wire [31:0] carry1;

assign sum1[15:0] = p0[15:0];

fulladd fa0 (sum1[16],carry1[0], p0[16],p1[0], p2[0]);
fulladd fa1 (sum1[17],carry1[1], p0[17],p1[1], p2[1]);
fulladd fa2 (sum1[18],carry1[2], p0[18],p1[2], p2[2]);
fulladd fa3 (sum1[19],carry1[3], p0[19],p1[3], p2[3]);
fulladd fa4 (sum1[20],carry1[4], p0[20],p1[4], p2[4]);
fulladd fa5 (sum1[21],carry1[5], p0[21],p1[5], p2[5]);
fulladd fa6 (sum1[22],carry1[6], p0[22],p1[6], p2[6]);
fulladd fa7 (sum1[23],carry1[7], p0[23],p1[7], p2[7]);
fulladd fa8 (sum1[24],carry1[8], p0[24],p1[8], p2[8]);
fulladd fa9 (sum1[25],carry1[9], p0[25],p1[9], p2[9]);
fulladd fa10(sum1[26],carry1[10],p0[26],p1[10],p2[10]);
fulladd fa11(sum1[27],carry1[11],p0[27],p1[11],p2[11]);
fulladd fa12(sum1[28],carry1[12],p0[28],p1[12],p2[12]);
fulladd fa13(sum1[29],carry1[13],p0[29],p1[13],p2[13]);
fulladd fa14(sum1[30],carry1[14],p0[30],p1[14],p2[14]);
fulladd fa15(sum1[31],carry1[15],p0[31],p1[15],p2[15]);

halfadd ha0(sum1[32],carry1[16],p1[16],p2[16]);
halfadd ha1(sum1[33],carry1[17],p1[17],p2[17]);
halfadd ha2(sum1[34],carry1[18],p1[18],p2[18]);
halfadd ha3(sum1[35],carry1[19],p1[19],p2[19]);
halfadd ha4(sum1[36],carry1[20],p1[20],p2[20]);
halfadd ha5(sum1[37],carry1[21],p1[21],p2[21]);
halfadd ha6(sum1[38],carry1[22],p1[22],p2[22]);
halfadd ha7(sum1[39],carry1[23],p1[23],p2[23]);
halfadd ha8(sum1[40],carry1[24], p1[24],p2[24]);
halfadd ha9(sum1[41],carry1[25], p1[25],p2[25]);
halfadd ha10(sum1[42],carry1[26],p1[26],p2[26]);
halfadd ha11(sum1[43],carry1[27],p1[27],p2[27]);
halfadd ha12(sum1[44],carry1[28],p1[28],p2[28]);
halfadd ha13(sum1[45],carry1[29],p1[29],p2[29]);
halfadd ha14(sum1[46],carry1[30],p1[30],p2[30]);
halfadd ha15(sum1[47],carry1[31],p1[31],p2[31]);

wire [63:0] sum2;
wire [35:0] carry2;

assign sum2[16:0] = sum1[16:0];
assign carry2[1:0] = 2'b00;

halfadd ha16(sum2[17],carry2[2],sum1[17],carry1[0]);
halfadd ha17(sum2[18],carry2[3],sum1[18],carry1[1]);
halfadd ha18(sum2[19],carry2[4],sum1[19],carry1[2]);
halfadd ha19(sum2[20],carry2[5],sum1[20],carry1[3]);
halfadd ha20(sum2[21],carry2[6],sum1[21],carry1[4]);
halfadd ha21(sum2[22],carry2[7],sum1[22],carry1[5]);
halfadd ha22(sum2[23],carry2[8],sum1[23],carry1[6]);
halfadd ha23(sum2[24],carry2[9],sum1[24], carry1[7]);
halfadd ha24(sum2[25],carry2[10],sum1[25],carry1[8]);
halfadd ha25(sum2[26],carry2[11],sum1[26],carry1[9]);
halfadd ha26(sum2[27],carry2[12],sum1[27],carry1[10]);
halfadd ha27(sum2[28],carry2[13],sum1[28],carry1[11]);
halfadd ha28(sum2[29],carry2[14],sum1[29],carry1[12]);
halfadd ha29(sum2[30],carry2[15],sum1[30],carry1[13]);
halfadd ha30(sum2[31],carry2[16],sum1[31],carry1[14]);

fulladd fa16(sum2[32],carry2[17],sum1[32],carry1[15],p3[0]);
fulladd fa17(sum2[33],carry2[18],sum1[33],carry1[16],p3[1]);
fulladd fa18(sum2[34],carry2[19],sum1[34],carry1[17],p3[2]);
fulladd fa19(sum2[35],carry2[20],sum1[35],carry1[18],p3[3]);
fulladd fa20(sum2[36],carry2[21],sum1[36],carry1[19],p3[4]);
fulladd fa21(sum2[37],carry2[22],sum1[37],carry1[20],p3[5]);
fulladd fa22(sum2[38],carry2[23],sum1[38],carry1[21],p3[6]);
fulladd fa23(sum2[39],carry2[24],sum1[39],carry1[22],p3[7]);
fulladd fa24(sum2[40],carry2[25],sum1[40],carry1[23],p3[8]);
fulladd fa25(sum2[41],carry2[26],sum1[41],carry1[24],p3[9]);
fulladd fa26(sum2[42],carry2[27],sum1[42],carry1[25],p3[10]);
fulladd fa27(sum2[43],carry2[28],sum1[43],carry1[26],p3[11]);
fulladd fa28(sum2[44],carry2[29],sum1[44],carry1[27],p3[12]);
fulladd fa29(sum2[45],carry2[30],sum1[45],carry1[28],p3[13]);
fulladd fa30(sum2[46],carry2[31],sum1[46],carry1[29],p3[14]);
fulladd fa31(sum2[47],carry2[32],sum1[47],carry1[30],p3[15]);

halfadd ha31(sum2[48],carry2[33],carry1[31],p3[16]);

assign sum2[63:49] = p3[31:17];
assign carry2 [35:34] = 2'b00;

// carry Lookahead Adder

wire carry_in;
wire c_in0,c_in1,c_in2,c_in3,c_in4,c_in5,c_in6,c_in7;

assign carry_in = 1'b0;
assign tProduct[15:0] = sum2[15:0];


clAdder cl0(tProduct[19:16],c_in0,sum2[19:16],carry2[3:0],carry_in);
clAdder cl1(tProduct[23:20],c_in1,sum2[23:20],carry2[7:4],c_in0);
clAdder cl2(tProduct[27:24],c_in2,sum2[27:24],carry2[11:8],c_in1);
clAdder cl3(tProduct[31:28],c_in3,sum2[31:28],carry2[15:12],c_in2);
clAdder cl4(tProduct[35:32],c_in4,sum2[35:32],carry2[19:16],c_in3);
clAdder cl5(tProduct[39:36],c_in5,sum2[39:36],carry2[23:20],c_in4);
clAdder cl6(tProduct[43:40],c_in6,sum2[43:40],carry2[27:24],c_in5);
clAdder cl7(tProduct[47:44],c_in7,sum2[47:44],carry2[31:28],c_in6);
clAdder cl8(tProduct[51:48],c_in8,sum2[51:48],carry2[35:32],c_in7);

assign tProduct[63:52] = sum2[63:52];



twosComp64 multwoscomp3(tcProduct,tProduct);

assign product=sign?( (operand2[31]^operand1[31]) ? tcProduct : tProduct) : tProduct;

endmodule


/*==================== Sixteen bit Multiplication ==============*/


module multiply16(product,a,b);

output [31:0] product;
input [15:0] a,b;


wire [15:0] p0,p1,p2,p3;

multiply8 m1(p0[15:0],a[7:0],b[7:0]);
multiply8 m2(p1[15:0],a[7:0],b[15:8]);
multiply8 m3(p2[15:0],a[15:8],b[7:0]);
multiply8 m4(p3[15:0],a[15:8],b[15:8]);

// carrysave adder 1

wire [23:0] sum1;
wire [15:0] carry1;

assign sum1[7:0] = p0[7:0];

fulladd fa0(sum1[8], carry1[0],p0[8], p1[0],p2[0]);
fulladd fa1(sum1[9], carry1[1],p0[9], p1[1],p2[1]);
fulladd fa2(sum1[10],carry1[2],p0[10],p1[2],p2[2]);
fulladd fa3(sum1[11],carry1[3],p0[11],p1[3],p2[3]);
fulladd fa4(sum1[12],carry1[4],p0[12],p1[4],p2[4]);
fulladd fa5(sum1[13],carry1[5],p0[13],p1[5],p2[5]);
fulladd fa6(sum1[14],carry1[6],p0[14],p1[6],p2[6]);
fulladd fa7(sum1[15],carry1[7],p0[15],p1[7],p2[7]);

halfadd ha0(sum1[16],carry1[8], p1[8], p2[8]);
halfadd ha1(sum1[17],carry1[9], p1[9], p2[9]);
halfadd ha2(sum1[18],carry1[10],p1[10],p2[10]);
halfadd ha3(sum1[19],carry1[11],p1[11],p2[11]);
halfadd ha4(sum1[20],carry1[12],p1[12],p2[12]);
halfadd ha5(sum1[21],carry1[13],p1[13],p2[13]);
halfadd ha6(sum1[22],carry1[14],p1[14],p2[14]);
halfadd ha7(sum1[23],carry1[15],p1[15],p2[15]);

wire [31:0] sum2;
wire [19:0] carry2;

assign sum2[8:0] = sum1[8:0];
assign carry2[1:0] = 2'b00;

halfadd ha8 (sum2[9], carry2[2],sum1[9], carry1[0]);
halfadd ha9 (sum2[10],carry2[3],sum1[10],carry1[1]);
halfadd ha10(sum2[11],carry2[4],sum1[11],carry1[2]);
halfadd ha11(sum2[12],carry2[5],sum1[12],carry1[3]);
halfadd ha12(sum2[13],carry2[6],sum1[13],carry1[4]);
halfadd ha13(sum2[14],carry2[7],sum1[14],carry1[5]);
halfadd ha14(sum2[15],carry2[8],sum1[15],carry1[6]);

fulladd fa8 (sum2[16],carry2[9], sum1[16],carry1[7], p3[0]);
fulladd fa9 (sum2[17],carry2[10],sum1[17],carry1[8], p3[1]);
fulladd fa10(sum2[18],carry2[11],sum1[18],carry1[9], p3[2]);
fulladd fa11(sum2[19],carry2[12],sum1[19],carry1[10],p3[3]);
fulladd fa12(sum2[20],carry2[13],sum1[20],carry1[11],p3[4]);
fulladd fa13(sum2[21],carry2[14],sum1[21],carry1[12],p3[5]);
fulladd fa14(sum2[22],carry2[15],sum1[22],carry1[13],p3[6]);
fulladd fa15(sum2[23],carry2[16],sum1[23],carry1[14],p3[7]);

halfadd ha15(sum2[24],carry2[17],carry1[15],p3[8]);

assign sum2[31:25] = p3[15:9];
assign carry2[19:18] = 2'b00;

// carry Lookahead Adder

wire carry_in;
wire c_in0,c_in1,c_in2,c_in3,c_in4;

assign carry_in = 1'b0;
assign product[7:0] = sum2[7:0];


clAdder cl0(product[11:8], c_in0,sum2[11:8], carry2[3:0],carry_in);
clAdder cl1(product[15:12],c_in1,sum2[15:12],carry2[7:4],c_in0);
clAdder cl2(product[19:16],c_in2,sum2[19:16],carry2[11:8],c_in1);
clAdder cl3(product[23:20],c_in3,sum2[23:20],carry2[15:12],c_in2);
clAdder cl4(product[27:24],c_in4,sum2[27:24],carry2[19:16],c_in3);

assign product[31:28] = sum2[31:28];
endmodule

//clAdder cl5(product[31:28],c_in3,sum2[31:28],carry2[15:12],c_in2);


/*==================== Eight bit Multiplication =============== */


module multiply8(product,a,b);

output [15:0] product;
input [7:0] a,b;


wire [7:0] p0,p1,p2,p3;

multiply4 m1(p0[7:0],a[3:0],b[3:0]);
multiply4 m2(p1[7:0],a[3:0],b[7:4]);
multiply4 m3(p2[7:0],a[7:4],b[3:0]);
multiply4 m4(p3[7:0],a[7:4],b[7:4]);

// carrysave adder 1

wire [11:0] sum1;
wire [7:0] carry1;

assign sum1[3:0] = p0[3:0];


fulladd fa0(sum1[4],carry1[0],p0[4],p1[0],p2[0]);
fulladd fa1(sum1[5],carry1[1],p0[5],p1[1],p2[1]);
fulladd fa2(sum1[6],carry1[2],p0[6],p1[2],p2[2]);
fulladd fa3(sum1[7],carry1[3],p0[7],p1[3],p2[3]);

halfadd ha0(sum1[8],carry1[4],p1[4],p2[4]);
halfadd ha1(sum1[9],carry1[5],p1[5],p2[5]);
halfadd ha2(sum1[10],carry1[6],p1[6],p2[6]);
halfadd ha3(sum1[11],carry1[7],p1[7],p2[7]);

wire [15:0] sum2;
wire [11:0] carry2;

assign sum2[4:0] = sum1[4:0];
assign carry2[1:0] = 2'b00;

halfadd ha4(sum2[5],carry2[2],sum1[5],carry1[0]);
halfadd ha5(sum2[6],carry2[3],sum1[6],carry1[1]);
halfadd ha6(sum2[7],carry2[4],sum1[7],carry1[2]);

fulladd fa4(sum2[8],carry2[5],sum1[8],carry1[3],p3[0]);
fulladd fa5(sum2[9],carry2[6],sum1[9],carry1[4],p3[1]);
fulladd fa6(sum2[10],carry2[7],sum1[10],carry1[5],p3[2]);
fulladd fa7(sum2[11],carry2[8],sum1[11],carry1[6],p3[3]);

halfadd ha7(sum2[12],carry2[9],carry1[7],p3[4]);

assign sum2[15:13] = p3[7:5];
assign carry2[11:10] = 2'b00;

// carry Save Adder

wire carry_in;
wire c_in0,c_in1,c_in2;

assign carry_in = 1'b0;
assign product[3:0] = sum2[3:0];


clAdder cl0(product[7:4],c_in0,sum2[7:4],carry2[3:0],carry_in);
clAdder cl1(product[11:8],c_in1,sum2[11:8],carry2[7:4],c_in0);
clAdder cl2(product[15:12],c_in2,sum2[15:12],carry2[11:8],c_in1);

endmodule

/*==================== Four bit Multiplier =============== */



module multiply4(product,a,b);

input [3:0] a,b;
output [7:0] product;

wire [3:0] w0,w1,w2,w3;
        // Here I am genetrating the Partial products are w0,w1,w2and w3
assign w0[3:0] = b[0] ? a[3:0] : 4'b0000;
assign w1[3:0] = b[1] ? a[3:0] : 4'b0000;
assign w2[3:0] = b[2] ? a[3:0] : 4'b0000;
assign w3[3:0] = b[3] ? a[3:0] : 4'b0000;

// Carry Save Adder 1

wire [5:0] sum1,carry1;

assign sum1[0] = w0[0];
assign carry1[0] = 1'b0;

halfadd ha0(sum1[1],carry1[1],w0[1],w1[0]);

fulladd fa0(sum1[2],carry1[2],w0[2],w1[1],w2[0]);
fulladd fa1(sum1[3],carry1[3],w0[3],w1[2],w2[1]);

halfadd ha1(sum1[4],carry1[4],w1[3],w2[2]);

assign sum1[5] = w2[3];
assign carry1[5] = 1'b0;


// Carry Save Adder 2

wire [7:0] sum2;
wire [7:0] carry2;

assign sum2[0] = sum1[0];
assign carry2[1:0] = 2'b00;

halfadd ha2(sum2[1],carry2[2],sum1[1],carry1[0]);
halfadd ha3(sum2[2],carry2[3],sum1[2],carry1[1]);

fulladd fa2(sum2[3],carry2[4],sum1[3],carry1[2],w3[0]);
fulladd fa3(sum2[4],carry2[5],sum1[4],carry1[3],w3[1]);
fulladd fa4(sum2[5],carry2[6],sum1[5],carry1[4],w3[2]);

halfadd ha4(sum2[6],carry2[7],carry1[5],w3[3]);

wire carry_in;
assign carry_in = 1'b0;
assign sum2[7] = 1'b0;

wire c_in0,c_in1;

clAdder cla0(product[3:0],c_in0,sum2[3:0],carry2[3:0],carry_in);
clAdder cla1(product[7:4],c_in1,sum2[7:4],carry2[7:4],c_in0);


endmodule

/*-------------------------------------------------------------------------------------------------*/
// Fout bit Paraller Adder Design using Carry Lookahead Method

module clAdder(sum,carry_out,a,b,carry_in);

output [3:0] sum;
output carry_out;
input [3:0] a,b;
input carry_in;

wire x0,a0,x1,a1,x2,a2,x3,a3;
wire c1,c2,c3,c4;

// performing "Exclusive-or" operation between the individual bits and assign to wire x

assign  x0 = a[0] ^ b[0],
        x1 = a[1] ^ b[1],
        x2 = a[2] ^ b[2],
        x3 = a[3] ^ b[3];

// performing "and" operation between the individual bits and assign to wire a

assign  a0 = a[0] & b[0],
        a1 = a[1] & b[1],
        a2 = a[2] & b[2],
        a3 = a[3] & b[3];

// computing the carry and assign to wire c

assign  c1 = a0 | (x0 & carry_in),
        c2 = a1 | (x1 & a0)|(x1 & x0 & carry_in),
        c3 = a2 | (x2 & a1)|(x2 & x1 & a0)|(x2 & x1 & x0 & carry_in),
        c4 = a3 | (x3 & a2)|(x3 & x2 & a1)|(x3 & x2 & x1 & a0)|(x3 & x2 & x1 & x0 & carry_in);

// computing sum

assign  sum[0] = x0 ^ carry_in,
        sum[1] = x1 ^ c1,
        sum[2] = x2 ^ c2,
        sum[3] = x3 ^ c3;

// assign the final carry output

assign carry_out = c4;

endmodule




/*-------------------------------------------------------------------------------------------------*/


// Full Adder Module

module fulladd(sum, carry, x,y,z);

output sum,carry;
input x,y,z;

wire w;
        assign   w = x ^ y;
        assign   sum = w ^ z;
        assign   carry = (x & y)|(w & z);
endmodule

/*-------------------------------------------------------------------------------------------------*/


// half Adder Module
module halfadd(sum, carry, x,y);

output sum,carry;
input x,y;

        assign   sum = x ^ y;
        assign   carry = x & y;

endmodule

/*-------------------------------------------------------------------------------------------------*/