www.pudn.com > x86.rar > fmul.v, change:2007-12-05,size:2375b


module fmul(out,in1,in2); 
 output [79:0] out; 
 reg	[79:0] out; 
 input  [79:0] in1; 
 input  [79:0] in2; 
 
 reg	[79:0] tproduct; 
 reg    [79:0] tproduct0; 
 reg	[15:0] cla161In1,cla161In2,cla162In1,cla162In2; 
 wire	[15:0] cla161Out,cla162Out; 
 reg	[15:0] exp,exp1; 
 wire	[16:1] cla161CarryOut,cla162CarryOut; 
 reg	[63:0] mulIn1,mulIn2; 
 wire 	[127:0] mulOut; 
 reg 	[63:0] tmul; 
 
 integer i; 
reg togle; 
reg sign; 
 
 
 cla16Bit cla16bitInst1(cla161Out,cla161CarryOut,cla161In1,cla161In2,1'b0); 
 cla16Bit cla16bitInst2(cla162Out,cla162CarryOut,cla162In1,cla162In2,1'b0); 
  mul64 mul64inst1(mulOut,mulIn1,mulIn2); 
 
  
 always @(in1 or in2 or cla161Out or cla162Out or cla162CarryOut) 
   begin 
     sign=1'b0; 
     tproduct0=80'b1; 
     if(|in1[78:0] == 1'b0) 
       tproduct0 = in1; 
     else if(|in2[78:0] == 1'b0) 
       tproduct0 = in2; 
     else 
       begin 
         cla161In1 = {1'b0,in1[78:64]}; 
         cla161In2 = {1'b0,in2[78:64]}; 
         cla162In1 = cla161Out; 
         cla162In2 = 16'd49154; 
         if(cla162Out[15] == 1'b1 || &cla162Out[14:0] == 1'b1) 
           begin 
             // report overflow 
		 
           end 
         else 
           begin 
             if(cla162CarryOut[16] == 1'b0 || |cla162Out[14:0] == 1'b0) 
               begin 
                 // report underflow  
		  
               end   
             else 
               begin 
		 
		 
                 // round the result in shiftout 
		exp=cla162Out[14:0]; 
		 
		togle=1'b1; 
		for(i=0; i<15;i=i+1)	// subtracting 1 from the cla16Out and storing into exp1 
		begin 
		   if(togle==1'b1) 
			begin 
			        if(cla162Out[i]==1'b1) 
				begin 
				togle=1'b0; 
				end 
				exp1[i]=~cla162Out[i]; 
   			end	 
		   else 
			exp1[i]=cla162Out[i]; 
		end 
 
		 
		mulIn1={1'b1,in1[62:0]}; 
		mulIn2={1'b1,in2[62:0]}; 
 
               end   
           end  
       end         
   end 
 
 
always @ (mulOut or exp or exp1 or sign or in1 or in2)// or twoscompout or cla163Out) 
begin 
	 
	tmul = (mulOut[127]) ? mulOut[127:64]: { mulOut[126:64],1'b0}; 
 
	if(mulOut[127]) 
	  tproduct[78:64]=exp[14:0]; 
	else 
	  tproduct[78:64]=exp1[14:0]; 
		 
	tproduct[63:0] = tmul[63:0]; 
	tproduct[79]=in1[79]^in2[79]; 
	 
	 
end 
 
always @(tproduct or tproduct0) 
begin 
if(|tproduct0==1'b0) 
out = tproduct0; 
else 
out = tproduct; 
 
end 
 
endmodule