www.pudn.com > x86.rar > fdiv.v, change:2007-12-05,size:2139b


module fdiv(out,in1,in2); 
 output [79:0] out; 
 reg	[79:0] out1; 
 input  [79:0] in1; 
 input  [79:0] in2; 
 
 reg	[79:0] tdiv; 
 reg	[79:0] tdiv0; 
 reg	[15:0] cla16In1,cla16In2; 
 wire	[15:0] cla16Out; 
 wire	[16:1] cla16CarryOut; 
 reg	[63:0] divIn1; 
 reg	[63:0] divIn2; 
 wire 	[127:0] divOut; 
wire	[15:0] twoscompout; 
 reg	[15:0] twoscompin; 
reg	[15:0] exp,exp1; 
reg  	togle; 
integer i; 
 
 
 
 cla16Bit cla16bitInst1(cla16Out,cla16CarryOut,cla16In1,cla16In2,1'b0); 
 division64 div64inst1(divIn1,divIn2,divOut,1'b0); 
 
assign out=(|tdiv0) ? tdiv0:tdiv; 
 
always @(in1 or in2) 
   begin  
			// This operation is same as exponent1 - exponent2 + Bias 
	     
            cla16In1 = {1'b0,in1[78:64]};	 
	    cla16In2 = { 1'b0, in2[78] , ~in2[77:64] }; 
   end 
 
always @(cla16Out or in1 or in2) 
begin 
	tdiv0=80'd1;	 
	if(|in1[78:0] == 1'b0) 
       tdiv0 = in1; 
     else if(|in2[78:0] == 1'b0) 
	begin 
       	 $display( "Overflow exception"); 
	end 
				//condition for underflow 
        if((in1[78]==1'b0 && in2[78]==1'b1 && cla16Out[14] == 1'b1) || |cla16Out[14:0] == 1'b0  )  
            begin 
             	$display ("under flow Exception"); 
            end 
            else 
	    begin			// condition for overflow 
	       if((in1[78]==1'b1 && in2[78]==1'b0 && cla16Out[14] == 1'b0) || &cla16Out[14:0] == 1'b1) 
               begin 
             	  $display ("Over flow Exception"); 
               end 
	       else 
               begin 
 
		exp=cla16Out[14:0]; 
		 
			// subtracting 1 from the cla16Out and storing into exp1 
		togle=1'b1; 
		for(i=0; i<15;i=i+1) 
		begin 
		   if(togle==1) 
			begin 
			        if(cla16Out[i]) 
				togle=1'b0; 
				exp1[i]=~cla16Out[i]; 
   			end	 
		   else 
			exp1[i]=cla16Out[i]; 
		end 
 
 
                divIn1=in1[63:0]; 
		divIn2=in2[63:0]; 
		 
               end   
           end  
        
   end 
 
always @(divOut or in1 or in2 or exp1 or exp) 
begin 
 
tdiv[79]=in1[79]^in2[79]; 
tdiv[63:0]=divOut[127] ? divOut[127:64]: {divOut[126:64],1'b0}; 
 
if(divOut[127]==1'b0) 
  tdiv[78:64]=exp1[14:0];   
else 
  tdiv[78:64]=exp[14:0]; 
end 
endmodule