www.pudn.com > x86.rar > division.v, change:2007-12-05,size:18938b


 
 
 
module division(dividend, divisor, divOut, signed1); 
input [63:0]dividend;  
input [31:0] divisor;  
input signed1;  
output [63:0]divOut;  
wire [63:0]divOut;  
  
wire [96:0] shiftIn;  
wire [96:0] shiftIn1, shiftIn2, shiftIn3, shiftIn4;  
wire [96:0] shiftIn5, shiftIn6, shiftIn7, shiftIn8;  
wire [96:0] shiftIn9, shiftIn10, shiftIn11, shiftIn12;  
wire [96:0] shiftIn13, shiftIn14, shiftIn15, shiftIn16;  
wire [96:0] shiftIn17, shiftIn18, shiftIn19, shiftIn20;  
wire [96:0] shiftIn21, shiftIn22, shiftIn23, shiftIn24;  
wire [96:0] shiftIn25, shiftIn26, shiftIn27, shiftIn28;  
wire [96:0] shiftIn29, shiftIn30, shiftIn31, shiftIn32;  
wire [96:0] shiftIn33, shiftIn34, shiftIn35, shiftIn36;  
wire [96:0] shiftIn37, shiftIn38, shiftIn39, shiftIn40;  
wire [96:0] shiftIn41, shiftIn42, shiftIn43, shiftIn44;  
wire [96:0] shiftIn45, shiftIn46, shiftIn47, shiftIn48;  
wire [96:0] shiftIn49, shiftIn50, shiftIn51, shiftIn52;  
wire [96:0] shiftIn53, shiftIn54, shiftIn55, shiftIn56;  
wire [96:0] shiftIn57, shiftIn58, shiftIn59, shiftIn60;  
wire [96:0] shiftIn61, shiftIn62, shiftIn63, shiftIn64;  
  
wire [32:0] B;  
  
wire [31:0] twosOut, twosOut1, twosOut2;  
wire [63:0] twosOut64;  
  
wire [96:0] shiftOut;  
wire [96:0] shiftOut1, shiftOut2, shiftOut3, shiftOut4;  
wire [96:0] shiftOut5, shiftOut6, shiftOut7, shiftOut8;  
wire [96:0] shiftOut9, shiftOut10, shiftOut11, shiftOut12;  
wire [96:0] shiftOut13, shiftOut14, shiftOut15, shiftOut16;  
wire [96:0] shiftOut17, shiftOut18, shiftOut19, shiftOut20;  
wire [96:0] shiftOut21, shiftOut22, shiftOut23, shiftOut24;  
wire [96:0] shiftOut25, shiftOut26, shiftOut27, shiftOut28;  
wire [96:0] shiftOut29, shiftOut30, shiftOut31, shiftOut32;  
wire [96:0] shiftOut33, shiftOut34, shiftOut35, shiftOut36;  
wire [96:0] shiftOut37, shiftOut38, shiftOut39, shiftOut40;  
wire [96:0] shiftOut41, shiftOut42, shiftOut43, shiftOut44;  
wire [96:0] shiftOut45, shiftOut46, shiftOut47, shiftOut48;  
wire [96:0] shiftOut49, shiftOut50, shiftOut51, shiftOut52;  
wire [96:0] shiftOut53, shiftOut54, shiftOut55, shiftOut56;  
wire [96:0] shiftOut57, shiftOut58, shiftOut59, shiftOut60;  
wire [96:0] shiftOut61, shiftOut62, shiftOut63, shiftOut64;  
  
  
wire [32:0] claOut1, claOut2, claOut3, claOut4, claOut5, claOut6, claOut7, claOut8;  
wire [32:0] claOut9, claOut10, claOut11, claOut12, claOut13, claOut14, claOut15, claOut16;  
wire [32:0] claOut17, claOut18, claOut19, claOut20, claOut21, claOut22, claOut23, claOut24;  
wire [32:0] claOut25, claOut26, claOut27, claOut28, claOut29, claOut30, claOut31, claOut32;  
wire [32:0] claOut33, claOut34, claOut35, claOut36, claOut37, claOut38, claOut39, claOut40;  
wire [32:0] claOut41, claOut42, claOut43, claOut44, claOut45, claOut46, claOut47, claOut48;  
wire [32:0] claOut49, claOut50, claOut51, claOut52, claOut53, claOut54, claOut55, claOut56;  
wire [32:0] claOut57, claOut58, claOut59, claOut60, claOut61, claOut62, claOut63, claOut64; 
wire [32:0] carry4syn;  
  
  
twosComp   twosCompInst1(twosOut, divisor[31:0]);  
twosComp   twosCompInst2(twosOut2, shiftIn64[31:0]);  
twosComp   twosCompInst3(twosOut1, shiftIn64[95:64]);  
twosComp64 twosComp64Inst1(twosOut64, dividend);  
  
cla33Bit cla33BitInst1( claOut1,carry4syn  , shiftOut[96:64], B, 1'b0);  
cla33Bit cla33BitInst2( claOut2,carry4syn , shiftOut1[96:64], B, 1'b0);  
cla33Bit cla33BitInst3( claOut3,carry4syn  , shiftOut2[96:64], B, 1'b0);  
cla33Bit cla33BitInst4( claOut4,carry4syn  , shiftOut3[96:64], B, 1'b0);  
cla33Bit cla33BitInst5( claOut5,carry4syn  , shiftOut4[96:64], B, 1'b0);  
cla33Bit cla33BitInst6( claOut6,carry4syn  , shiftOut5[96:64], B, 1'b0);  
cla33Bit cla33BitInst7( claOut7,carry4syn  , shiftOut6[96:64], B, 1'b0);  
cla33Bit cla33BitInst8( claOut8,carry4syn  , shiftOut7[96:64], B, 1'b0);  
cla33Bit cla33BitInst9( claOut9,carry4syn  , shiftOut8[96:64], B, 1'b0);  
cla33Bit cla33BitInst10( claOut10,carry4syn  , shiftOut9[96:64], B, 1'b0);  
cla33Bit cla33BitInst11( claOut11,carry4syn  , shiftOut10[96:64], B, 1'b0);  
cla33Bit cla33BitInst12( claOut12,carry4syn  , shiftOut11[96:64], B, 1'b0);  
cla33Bit cla33BitInst13( claOut13,carry4syn  , shiftOut12[96:64], B, 1'b0);  
cla33Bit cla33BitInst14( claOut14,carry4syn  , shiftOut13[96:64], B, 1'b0);  
cla33Bit cla33BitInst15( claOut15,carry4syn  , shiftOut14[96:64], B, 1'b0);  
cla33Bit cla33BitInst16( claOut16,carry4syn  , shiftOut15[96:64], B, 1'b0);  
cla33Bit cla33BitInst17( claOut17,carry4syn  , shiftOut16[96:64], B, 1'b0);  
cla33Bit cla33BitInst18( claOut18,carry4syn  , shiftOut17[96:64], B, 1'b0);  
cla33Bit cla33BitInst19( claOut19,carry4syn  , shiftOut18[96:64], B, 1'b0);  
cla33Bit cla33BitInst20( claOut20,carry4syn  , shiftOut19[96:64], B, 1'b0);  
cla33Bit cla33BitInst21( claOut21,carry4syn  , shiftOut20[96:64], B, 1'b0);  
cla33Bit cla33BitInst22( claOut22,carry4syn  , shiftOut21[96:64], B, 1'b0);  
cla33Bit cla33BitInst23( claOut23,carry4syn  , shiftOut22[96:64], B, 1'b0);  
cla33Bit cla33BitInst24( claOut24,carry4syn  , shiftOut23[96:64], B, 1'b0);  
cla33Bit cla33BitInst25( claOut25,carry4syn  , shiftOut24[96:64], B, 1'b0);  
cla33Bit cla33BitInst26( claOut26,carry4syn  , shiftOut25[96:64], B, 1'b0);  
cla33Bit cla33BitInst27( claOut27,carry4syn  , shiftOut26[96:64], B, 1'b0);  
cla33Bit cla33BitInst28( claOut28,carry4syn  , shiftOut27[96:64], B, 1'b0);  
cla33Bit cla33BitInst29( claOut29,carry4syn  , shiftOut28[96:64], B, 1'b0);  
cla33Bit cla33BitInst30( claOut30,carry4syn  , shiftOut29[96:64], B, 1'b0);  
cla33Bit cla33BitInst31( claOut31,carry4syn  , shiftOut30[96:64], B, 1'b0);  
cla33Bit cla33BitInst32( claOut32,carry4syn  , shiftOut31[96:64], B, 1'b0);  
cla33Bit cla33BitInst33( claOut33,carry4syn  , shiftOut32[96:64], B, 1'b0);  
cla33Bit cla33BitInst34( claOut34,carry4syn  , shiftOut33[96:64], B, 1'b0);  
cla33Bit cla33BitInst35( claOut35,carry4syn , shiftOut34[96:64], B, 1'b0);  
cla33Bit cla33BitInst36( claOut36,carry4syn  , shiftOut35[96:64], B, 1'b0);  
cla33Bit cla33BitInst37( claOut37,carry4syn  , shiftOut36[96:64], B, 1'b0);  
cla33Bit cla33BitInst38( claOut38,carry4syn  , shiftOut37[96:64], B, 1'b0);  
cla33Bit cla33BitInst39( claOut39,carry4syn  , shiftOut38[96:64], B, 1'b0);  
cla33Bit cla33BitInst40( claOut40,carry4syn  , shiftOut39[96:64], B, 1'b0);  
cla33Bit cla33BitInst41( claOut41,carry4syn  , shiftOut40[96:64], B, 1'b0);  
cla33Bit cla33BitInst42( claOut42, carry4syn , shiftOut41[96:64], B, 1'b0);  
cla33Bit cla33BitInst43( claOut43, carry4syn , shiftOut42[96:64], B, 1'b0);  
cla33Bit cla33BitInst44( claOut44, carry4syn , shiftOut43[96:64], B, 1'b0);  
cla33Bit cla33BitInst45( claOut45, carry4syn , shiftOut44[96:64], B, 1'b0);  
cla33Bit cla33BitInst46( claOut46, carry4syn , shiftOut45[96:64], B, 1'b0);  
cla33Bit cla33BitInst47( claOut47, carry4syn , shiftOut46[96:64], B, 1'b0);  
cla33Bit cla33BitInst48( claOut48, carry4syn , shiftOut47[96:64], B, 1'b0);  
cla33Bit cla33BitInst49( claOut49, carry4syn , shiftOut48[96:64], B, 1'b0);  
cla33Bit cla33BitInst50( claOut50, carry4syn , shiftOut49[96:64], B, 1'b0);  
cla33Bit cla33BitInst51( claOut51, carry4syn , shiftOut50[96:64], B, 1'b0);  
cla33Bit cla33BitInst52( claOut52, carry4syn , shiftOut51[96:64], B, 1'b0);  
cla33Bit cla33BitInst53( claOut53, carry4syn , shiftOut52[96:64], B, 1'b0);  
cla33Bit cla33BitInst54( claOut54, carry4syn , shiftOut53[96:64], B, 1'b0);  
cla33Bit cla33BitInst55( claOut55, carry4syn , shiftOut54[96:64], B, 1'b0);  
cla33Bit cla33BitInst56( claOut56, carry4syn , shiftOut55[96:64], B, 1'b0);  
cla33Bit cla33BitInst57( claOut57, carry4syn , shiftOut56[96:64], B, 1'b0);  
cla33Bit cla33BitInst58( claOut58, carry4syn , shiftOut57[96:64], B, 1'b0);  
cla33Bit cla33BitInst59( claOut59, carry4syn , shiftOut58[96:64], B, 1'b0);  
cla33Bit cla33BitInst60( claOut60, carry4syn , shiftOut59[96:64], B, 1'b0);  
cla33Bit cla33BitInst61( claOut61, carry4syn , shiftOut60[96:64], B, 1'b0);  
cla33Bit cla33BitInst62( claOut62, carry4syn , shiftOut61[96:64], B, 1'b0);  
cla33Bit cla33BitInst63( claOut63, carry4syn , shiftOut62[96:64], B, 1'b0);  
cla33Bit cla33BitInst64( claOut64, carry4syn , shiftOut63[96:64], B, 1'b0);  
  
shifter96Bit shifter96BitInst0(shiftOut, shiftIn, 1'b1);  
shifter96Bit shifter96BitInst1(shiftOut1, shiftIn1, 1'b1);  
shifter96Bit shifter96BitInst2(shiftOut2, shiftIn2, 1'b1);  
shifter96Bit shifter96BitInst3(shiftOut3, shiftIn3, 1'b1);  
shifter96Bit shifter96BitInst4(shiftOut4, shiftIn4, 1'b1);  
shifter96Bit shifter96BitInst5(shiftOut5, shiftIn5, 1'b1);  
shifter96Bit shifter96BitInst6(shiftOut6, shiftIn6, 1'b1);  
shifter96Bit shifter96BitInst7(shiftOut7, shiftIn7, 1'b1);  
shifter96Bit shifter96BitInst8(shiftOut8, shiftIn8, 1'b1);  
shifter96Bit shifter96BitInst9(shiftOut9, shiftIn9, 1'b1);  
shifter96Bit shifter96BitInst10(shiftOut10, shiftIn10, 1'b1);  
shifter96Bit shifter96BitInst11(shiftOut11, shiftIn11, 1'b1);  
shifter96Bit shifter96BitInst12(shiftOut12, shiftIn12, 1'b1);  
shifter96Bit shifter96BitInst13(shiftOut13, shiftIn13, 1'b1);  
shifter96Bit shifter96BitInst14(shiftOut14, shiftIn14, 1'b1);  
shifter96Bit shifter96BitInst15(shiftOut15, shiftIn15, 1'b1);  
shifter96Bit shifter96BitInst16(shiftOut16, shiftIn16, 1'b1);  
shifter96Bit shifter96BitInst17(shiftOut17, shiftIn17, 1'b1);  
shifter96Bit shifter96BitInst18(shiftOut18, shiftIn18, 1'b1);  
shifter96Bit shifter96BitInst19(shiftOut19, shiftIn19, 1'b1);  
shifter96Bit shifter96BitInst20(shiftOut20, shiftIn20, 1'b1);  
shifter96Bit shifter96BitInst21(shiftOut21, shiftIn21, 1'b1);  
shifter96Bit shifter96BitInst22(shiftOut22, shiftIn22, 1'b1);  
shifter96Bit shifter96BitInst23(shiftOut23, shiftIn23, 1'b1);  
shifter96Bit shifter96BitInst24(shiftOut24, shiftIn24, 1'b1);  
shifter96Bit shifter96BitInst25(shiftOut25, shiftIn25, 1'b1);  
shifter96Bit shifter96BitInst26(shiftOut26, shiftIn26, 1'b1);  
shifter96Bit shifter96BitInst27(shiftOut27, shiftIn27, 1'b1);  
shifter96Bit shifter96BitInst28(shiftOut28, shiftIn28, 1'b1);  
shifter96Bit shifter96BitInst29(shiftOut29, shiftIn29, 1'b1);  
shifter96Bit shifter96BitInst30(shiftOut30, shiftIn30, 1'b1);  
shifter96Bit shifter96BitInst31(shiftOut31, shiftIn31, 1'b1);  
shifter96Bit shifter96BitInst32(shiftOut32, shiftIn32, 1'b1);  
shifter96Bit shifter96BitInst33(shiftOut33, shiftIn33, 1'b1);  
shifter96Bit shifter96BitInst34(shiftOut34, shiftIn34, 1'b1);  
shifter96Bit shifter96BitInst35(shiftOut35, shiftIn35, 1'b1);  
shifter96Bit shifter96BitInst36(shiftOut36, shiftIn36, 1'b1);  
shifter96Bit shifter96BitInst37(shiftOut37, shiftIn37, 1'b1);  
shifter96Bit shifter96BitInst38(shiftOut38, shiftIn38, 1'b1);  
shifter96Bit shifter96BitInst39(shiftOut39, shiftIn39, 1'b1);  
shifter96Bit shifter96BitInst40(shiftOut40, shiftIn40, 1'b1);  
shifter96Bit shifter96BitInst41(shiftOut41, shiftIn41, 1'b1);  
shifter96Bit shifter96BitInst42(shiftOut42, shiftIn42, 1'b1);  
shifter96Bit shifter96BitInst43(shiftOut43, shiftIn43, 1'b1);  
shifter96Bit shifter96BitInst44(shiftOut44, shiftIn44, 1'b1);  
shifter96Bit shifter96BitInst45(shiftOut45, shiftIn45, 1'b1);  
shifter96Bit shifter96BitInst46(shiftOut46, shiftIn46, 1'b1);  
shifter96Bit shifter96BitInst47(shiftOut47, shiftIn47, 1'b1);  
shifter96Bit shifter96BitInst48(shiftOut48, shiftIn48, 1'b1);  
shifter96Bit shifter96BitInst49(shiftOut49, shiftIn49, 1'b1);  
shifter96Bit shifter96BitInst50(shiftOut50, shiftIn50, 1'b1);  
shifter96Bit shifter96BitInst51(shiftOut51, shiftIn51, 1'b1);  
shifter96Bit shifter96BitInst52(shiftOut52, shiftIn52, 1'b1);  
shifter96Bit shifter96BitInst53(shiftOut53, shiftIn53, 1'b1);  
shifter96Bit shifter96BitInst54(shiftOut54, shiftIn54, 1'b1);  
shifter96Bit shifter96BitInst55(shiftOut55, shiftIn55, 1'b1);  
shifter96Bit shifter96BitInst56(shiftOut56, shiftIn56, 1'b1);  
shifter96Bit shifter96BitInst57(shiftOut57, shiftIn57, 1'b1);  
shifter96Bit shifter96BitInst58(shiftOut58, shiftIn58, 1'b1);  
shifter96Bit shifter96BitInst59(shiftOut59, shiftIn59, 1'b1);  
shifter96Bit shifter96BitInst60(shiftOut60, shiftIn60, 1'b1);  
shifter96Bit shifter96BitInst61(shiftOut61, shiftIn61, 1'b1);  
shifter96Bit shifter96BitInst62(shiftOut62, shiftIn62, 1'b1);  
shifter96Bit shifter96BitInst63(shiftOut63, shiftIn63, 1'b1);  
shifter96Bit shifter96BitInst64(shiftOut64, shiftIn64, 1'b1);  
shifter96Bit shifter96BitInst65(/*shiftOut65*/ , shiftOut64, 1'b0);  
  
assign  B[31:0]       = (signed1 == 1'b0) ? twosOut : ( divisor[31] == 1'b1 ? divisor: twosOut);  
assign  B[32]         = 1'b1;  
assign  shiftIn = (signed1 == 1'b0)? {33'd0, dividend } : (dividend[63] == 1'b1 ? {33'h0,twosOut64}:{33'h0,dividend}) ;  
  
assign shiftIn1  = (claOut1[32]  )? shiftOut   : {claOut1,shiftOut[63:1],1'b1};  
assign shiftIn2  = (claOut2[32]  )? shiftOut1  : {claOut2,shiftOut1[63:1],1'b1};  
assign shiftIn3  = (claOut3[32]  )? shiftOut2  : {claOut3,shiftOut2[63:1],1'b1};  
assign shiftIn4  = (claOut4[32]  )? shiftOut3  : {claOut4,shiftOut3[63:1],1'b1};  
assign shiftIn5  = (claOut5[32]  )? shiftOut4  : {claOut5,shiftOut4[63:1],1'b1};  
assign shiftIn6  = (claOut6[32]  )? shiftOut5  : {claOut6,shiftOut5[63:1],1'b1};  
assign shiftIn7  = (claOut7[32]  )? shiftOut6  : {claOut7,shiftOut6[63:1],1'b1};  
assign shiftIn8  = (claOut8[32]  )? shiftOut7  : {claOut8,shiftOut7[63:1],1'b1};  
assign shiftIn9  = (claOut9[32]  )? shiftOut8  : {claOut9,shiftOut8[63:1],1'b1};  
assign shiftIn10 = (claOut10[32] )? shiftOut9  : {claOut10,shiftOut9[63:1],1'b1};  
assign shiftIn11 = (claOut11[32] )? shiftOut10 : {claOut11,shiftOut10[63:1],1'b1};  
assign shiftIn12 = (claOut12[32] )? shiftOut11 : {claOut12,shiftOut11[63:1],1'b1};  
assign shiftIn13 = (claOut13[32] )? shiftOut12 : {claOut13,shiftOut12[63:1],1'b1};  
assign shiftIn14 = (claOut14[32] )? shiftOut13 : {claOut14,shiftOut13[63:1],1'b1};  
assign shiftIn15 = (claOut15[32] )? shiftOut14 : {claOut15,shiftOut14[63:1],1'b1};  
assign shiftIn16 = (claOut16[32] )? shiftOut15 : {claOut16,shiftOut15[63:1],1'b1};  
assign shiftIn17 = (claOut17[32] )? shiftOut16 : {claOut17,shiftOut16[63:1],1'b1};  
assign shiftIn18 = (claOut18[32] )? shiftOut17 : {claOut18,shiftOut17[63:1],1'b1};  
assign shiftIn19 = (claOut19[32] )? shiftOut18 : {claOut19,shiftOut18[63:1],1'b1};  
assign shiftIn20 = (claOut20[32] )? shiftOut19 : {claOut20,shiftOut19[63:1],1'b1};  
assign shiftIn21 = (claOut21[32] )? shiftOut20 : {claOut21,shiftOut20[63:1],1'b1};  
assign shiftIn22 = (claOut22[32] )? shiftOut21 : {claOut22,shiftOut21[63:1],1'b1};  
assign shiftIn23 = (claOut23[32] )? shiftOut22 : {claOut23,shiftOut22[63:1],1'b1};  
assign shiftIn24 = (claOut24[32] )? shiftOut23 : {claOut24,shiftOut23[63:1],1'b1};  
assign shiftIn25 = (claOut25[32] )? shiftOut24 : {claOut25,shiftOut24[63:1],1'b1};  
assign shiftIn26 = (claOut26[32] )? shiftOut25 : {claOut26,shiftOut25[63:1],1'b1};  
assign shiftIn27 = (claOut27[32] )? shiftOut26 : {claOut27,shiftOut26[63:1],1'b1};  
assign shiftIn28 = (claOut28[32] )? shiftOut27 : {claOut28,shiftOut27[63:1],1'b1};  
assign shiftIn29 = (claOut29[32] )? shiftOut28 : {claOut29,shiftOut28[63:1],1'b1};  
assign shiftIn30 = (claOut30[32] )? shiftOut29 : {claOut30,shiftOut29[63:1],1'b1};  
assign shiftIn31 = (claOut31[32] )? shiftOut30 : {claOut31,shiftOut30[63:1],1'b1};  
assign shiftIn32 = (claOut32[32] )? shiftOut31 : {claOut32,shiftOut31[63:1],1'b1};  
assign shiftIn33 = (claOut33[32] )? shiftOut32 : {claOut33,shiftOut32[63:1],1'b1};  
assign shiftIn34 = (claOut34[32] )? shiftOut33 : {claOut34,shiftOut33[63:1],1'b1};  
assign shiftIn35 = (claOut35[32] )? shiftOut34 : {claOut35,shiftOut34[63:1],1'b1};  
assign shiftIn36 = (claOut36[32] )? shiftOut35 : {claOut36,shiftOut35[63:1],1'b1};  
assign shiftIn37 = (claOut37[32] )? shiftOut36 : {claOut37,shiftOut36[63:1],1'b1};  
assign shiftIn38 = (claOut38[32] )? shiftOut37 : {claOut38,shiftOut37[63:1],1'b1};  
assign shiftIn39 = (claOut39[32] )? shiftOut38 : {claOut39,shiftOut38[63:1],1'b1};  
assign shiftIn40 = (claOut40[32] )? shiftOut39 : {claOut40,shiftOut39[63:1],1'b1};  
assign shiftIn41 = (claOut41[32] )? shiftOut40 : {claOut41,shiftOut40[63:1],1'b1};  
assign shiftIn42 = (claOut42[32] )? shiftOut41 : {claOut42,shiftOut41[63:1],1'b1};  
assign shiftIn43 = (claOut43[32] )? shiftOut42 : {claOut43,shiftOut42[63:1],1'b1};  
assign shiftIn44 = (claOut44[32] )? shiftOut43 : {claOut44,shiftOut43[63:1],1'b1};  
assign shiftIn45 = (claOut45[32] )? shiftOut44 : {claOut45,shiftOut44[63:1],1'b1};  
assign shiftIn46 = (claOut46[32] )? shiftOut45 : {claOut46,shiftOut45[63:1],1'b1};  
assign shiftIn47 = (claOut47[32] )? shiftOut46 : {claOut47,shiftOut46[63:1],1'b1};  
assign shiftIn48 = (claOut48[32] )? shiftOut47 : {claOut48,shiftOut47[63:1],1'b1};  
assign shiftIn49 = (claOut49[32] )? shiftOut48 : {claOut49,shiftOut48[63:1],1'b1};  
assign shiftIn50 = (claOut50[32] )? shiftOut49 : {claOut50,shiftOut49[63:1],1'b1};  
assign shiftIn51 = (claOut51[32] )? shiftOut50 : {claOut51,shiftOut50[63:1],1'b1};  
assign shiftIn52 = (claOut52[32] )? shiftOut51 : {claOut52,shiftOut51[63:1],1'b1};  
assign shiftIn53 = (claOut53[32] )? shiftOut52 : {claOut53,shiftOut52[63:1],1'b1};  
assign shiftIn54 = (claOut54[32] )? shiftOut53 : {claOut54,shiftOut53[63:1],1'b1};  
assign shiftIn55 = (claOut55[32] )? shiftOut54 : {claOut55,shiftOut54[63:1],1'b1};  
assign shiftIn56 = (claOut56[32] )? shiftOut55 : {claOut56,shiftOut55[63:1],1'b1};  
assign shiftIn57 = (claOut57[32] )? shiftOut56 : {claOut57,shiftOut56[63:1],1'b1};  
assign shiftIn58 = (claOut58[32] )? shiftOut57 : {claOut58,shiftOut57[63:1],1'b1};  
assign shiftIn59 = (claOut59[32] )? shiftOut58 : {claOut59,shiftOut58[63:1],1'b1};  
assign shiftIn60 = (claOut60[32] )? shiftOut59 : {claOut60,shiftOut59[63:1],1'b1};  
assign shiftIn61 = (claOut61[32] )? shiftOut60 : {claOut61,shiftOut60[63:1],1'b1};  
assign shiftIn62 = (claOut62[32] )? shiftOut61 : {claOut62,shiftOut61[63:1],1'b1};  
assign shiftIn63 = (claOut63[32] )? shiftOut62 : {claOut63,shiftOut62[63:1],1'b1};  
assign shiftIn64 = (claOut64[32] )? shiftOut63 : {claOut64,shiftOut63[63:1],1'b1};  
  
assign divOut[31:0]  = (signed1 == 1'b0)? shiftIn64[95:64]: (dividend[63] == 1'b0 ? shiftIn64[95:64] : twosOut1);  
assign divOut[63:32] = (signed1 == 1'b0)? shiftIn64[31:0] : (dividend[63] == divisor[31] ? shiftIn64[31:0] : twosOut2);  
  
endmodule  
  
 
module shifter96Bit(shiftOut, shiftIn, direction);  
input [96:0]shiftIn;  
input direction;  
output [96:0] shiftOut;  
assign shiftOut = (direction)? ({shiftIn[95:0], 1'b0}):  
                         ({1'b0, shiftIn[96:1]});  
endmodule  
  
  
  
 
module cla33Bit(claOut,carryOut,in1,in2,carry);  
input [32:0] in1,in2;  
input carry;  
output [32:0] claOut,carryOut;  
cla32Bit cla32BitInst(claOut[31:0],carryOut[31:0],in1[31:0],in2[31:0],carry);  
assign claOut[32] = in1[32] ^ in2[32] ^ carryOut[31];  
assign carryOut[32] = ((in1[32] & in2[32]) | (in2[32] & carryOut[31]) | (in1[32] & carryOut[31]));  
endmodule