www.pudn.com > x86.rar > conUnitWrapper.v, change:2007-12-05,size:13977b


module conUnitWrapper(mode,oPbits,context_out,nextIns,address,clk,reset,ready,op1,op2,op1Type,op2Type,opSize,adSize,operation,context_in,eflags_in,eflags_out,size,flush,oldPC,newPC,StatWordIn,StatWordOut,CntrlWordIn,CntrlWordOut,TagWordIn,TagWordOut,LastInsPtrIn,LastDatPtrIn,LastOpCodeIn_Context,LastOpCodeIn_Decoder,LastInsPtrOut,LastDatPtrOut,LastOpCodeOut,memData,memAddr,Rw,memEnable,ack,MxcsrIn,MxcsrOut,MMUcmd,PE);

output          mode;
output  [3:0]   oPbits;                 // to CI for selecting part of data i/o lines position
output  [271:0] context_out;            // Output to the context infrastructure
output  [55:0]  address;                        // Output to context, to request for read / write of specific wireisters
output          nextIns;                                // Output to decoder to begin decode of next instruction
output  [31:0]  eflags_out;
output  [8:0]   size;
output          flush;
output  [31:0]  newPC;
output  [15:0]  StatWordOut;
output  [15:0]  CntrlWordOut;
output  [15:0]  TagWordOut;
output  [47:0]  LastInsPtrOut;
output  [47:0]  LastDatPtrOut;
output  [10:0]  LastOpCodeOut;
output  [31:0]  MxcsrOut;
output  [31:0]  memAddr;
output          Rw;
output          memEnable;
output  [7:0]   MMUcmd;



inout  [31:0]   memData;


//input  PE;ConUnitWrapper.v

input  [15:0]   StatWordIn;
input  [15:0]   CntrlWordIn;
input  [15:0]   TagWordIn;
input  [47:0]   LastInsPtrIn;
input  [47:0]   LastDatPtrIn;
input  [10:0]   LastOpCodeIn_Context;
input  [10:0]   LastOpCodeIn_Decoder;
input  [31:0]   MxcsrIn;
input  [31:0]   oldPC;
input  [31:0]   eflags_in;                      // Eflags_out from ALU to this module, Eflags_in from context to this module
input  [31:0]   op1;                    // Decoder operand inputs
input  [31:0]   op2;
input  [17:0]   op1Type;                // Decoder inputs, operand addressing mode specifier
input  [17:0]   op2Type;
input  [2:0]    opSize;                 // Decoder input - operand size specifier 8/16/32/64
input           adSize;                         // Decoder input - address size specifier
input  [10:0]   operation;                      // Decoder input, passed on to ALU to indicate a specific operation
input  [271:0]  context_in;             // Input from context infrastructure
input           clk;
input           reset;
input           ready;                          // Input from decoder to start fetching operands
input           ack;
input           PE;

wire    [31:0]  memAddr;
wire    [31:0]  in1;                    // Inputs to the integer ALU, calculated here
wire    [31:0]  in2;
wire    [31:0]  in3;
wire    [63:0]  inm1;                   // inputs to MMX ALU
wire    [63:0]  inm2;
wire    [79:0]   infp1;                 // inputs to FPU ALU
wire    [79:0]  infp2;
wire    [127:0] insse1_1;
wire    [127:0] insse1_2;
wire    [127:0] insse1_3;
wire    [127:0] insse2_1;
wire    [127:0] insse2_2;
wire    [127:0] insse3_1;
wire    [127:0] insse3_2;

wire    [7:0]   insse2_3;
wire    [7:0]   insse3_3;
wire            enableintalu;                   // 1 -  enable ALU      0 - disable ALU
wire            enablemmxalu;                   //
wire            enablefpualu;                   //
wire            enablessealu;
wire            enablesse2alu;
wire            enablesse3alu;
wire   [63:0]   out;                            //  integer ALU o/p
wire   [63:0]   outm;                   //  MMX ALU o/p
wire   [159:0]  outfp;                  //  FPU ALU o/p
wire   [127:0]  outsse1;
wire   [127:0]  outsse2;
wire   [127:0]  outsse3;
                // memory lines writing
wire   [31:0]   eflags_outint,eflags_outfpu;
wire   [255:0]  result;
wire   [10:0]   newOperation;

// State variables for FSM operation - see the documentation for the FSM details



wire    [15:0]  cwIn;
wire    [15:0]  swIn;
wire    [15:0]  twIn;
wire    [47:0]  lipIn;
wire    [47:0]  ldpIn;
wire    [10:0]  lopIn;
wire    [2:0]   Op1_Tag;
wire    [2:0]   Op2_Tag;
wire    [31:0] alunewPC;

// Signals to and from Control Unit real mode
wire            rmode;
wire    [3:0]   roPbits;
wire    [271:0] rcontext_out;
wire    [55:0]  raddress;
wire    [8:0]   rsize;
wire            rnextIns;
wire    [31:0]  rmemAddr;
wire            rRw;
wire            rmemEnable;
wire    [15:0]  rcwIn;
wire    [15:0]  rswIn;
wire    [15:0]  rtwIn;
wire    [47:0]  rlipIn;
wire    [47:0]  rldpIn;
wire    [10:0]  rlopIn;
wire            renableintalu;
wire            renablemmxalu;
wire            renablefpualu;
wire            renablessealu;
wire            renablesse2alu;
wire            renablesse3alu;
wire    [2:0]   rOp1_Tag;
wire    [2:0]   rOp2_Tag;
wire    [31:0]  rin1;
wire    [31:0]  rin2;
wire    [31:0]  rin3;
wire    [79:0]  rinfp1;
wire    [79:0]  rinfp2;
wire    [63:0]  rinm1;
wire    [63:0]  rinm2;
wire    [127:0] rinsse1_1;
wire    [127:0] rinsse1_2;
wire    [127:0] rinsse1_3;
wire    [127:0] rinsse2_1;
wire    [127:0] rinsse2_2;
wire    [7:0]           rinsse2_3;
wire    [127:0] rinsse3_1;
wire    [127:0] rinsse3_2;
wire    [7:0]           rinsse3_3;
wire    [10:0]  rnewOperation;
wire    [31:0]  rmemData;
wire    [7:0]   rVect;
wire            rExceptionEnable;
wire    [31:0]  rnewPC;
wire            rflush;
wire    [31:0]  reflags_out;

//Signals to and from Control Unit Protected mode
wire            pmode;
wire    [3:0]   poPbits;
wire    [271:0] pcontext_out;
wire    [55:0]  paddress;
wire    [8:0]   psize;
wire            pnextIns;
wire    [31:0]  pmemAddr;
wire            pRw;
wire            pmemEnable;
wire    [15:0]  pcwIn;
wire    [15:0]  pswIn;
wire    [15:0]  ptwIn;
wire    [47:0]  plipIn;
wire    [47:0]  pldpIn;
wire    [10:0]  plopIn;
wire            penableintalu;
wire            penablemmxalu;
wire            penablefpualu;
wire            penablessealu;
wire            penablesse2alu;
wire            penablesse3alu;
wire    [2:0]   pOp1_Tag;
wire    [2:0]   pOp2_Tag;
wire    [31:0]  pin1;
wire    [31:0]  pin2;
wire    [31:0]  pin3;
wire    [79:0]  pinfp1;
wire    [79:0]  pinfp2;
wire    [63:0]  pinm1;
wire    [63:0]  pinm2;
wire    [127:0] pinsse1_1;
wire    [127:0] pinsse1_2;
wire    [127:0] pinsse1_3;
wire    [127:0] pinsse2_1;
wire    [127:0] pinsse2_2;
wire    [7:0]           pinsse2_3;
wire    [127:0] pinsse3_1;
wire    [127:0] pinsse3_2;
wire    [7:0]           pinsse3_3;

wire    [31:0]  pmemData;

wire    [7:0]   pVect;
wire            pExceptionEnable;
wire    [31:0]  pnewPC;
wire            pflush;
wire            penableTaskSwitch;
wire    [15:0]  pDesSel;

// signals of Exception Handling module
wire [31:0] ememData;
wire [31:0] ememAddr;
wire        ememEnable ;
wire [271:0] econtext_out;
wire emode ;
wire [31:0] eflags_exception;
wire [7:0] eVect;
wire ePCflush;
wire ExceptionAck;
wire [55:0] econtext_addr;
wire [8:0] op_size; // specifies register size
wire [31:0] eoutPC;
wire [1:0] outEIPsize;
wire ExceptionEnable;
wire eExceptionEnable;
wire            ememRw;
wire            eenableTS;
wire    [15:0]  eTSSsegsel;


//Signal for Task Switch module
wire            enableTaskSwitch;
wire    [15:0]  DesSel;
wire            TaskSwitchOver;

wire    [271:0] tscontext_out;
wire    [55:0]  tsaddress;
wire            tsflush;
wire    [31:0]  tsnewPC;
wire    [8:0]   tssize;
wire    [31:0]  tsmemData;
wire    [31:0]  tsmemAddr;
wire            tsmemRw;
wire            tsmemEnable;
wire            tsmode;
wire            tsExceptionEnable;
wire    [7:0]   tsVect;
wire    [31:0]  tseflags_out;
wire            aluflush;


//Multiplexing Task Switch signals
assign  enableTaskSwitch = ExceptionEnable ?  eenableTS : penableTaskSwitch;
assign  DesSel = ExceptionEnable ? eTSSsegsel : pDesSel;

//Multiplexing Context Infrastructure signals
assign  mode =ExceptionEnable?emode : (PE ? (enableTaskSwitch? tsmode:pmode) : rmode);
assign  oPbits= PE ? poPbits : roPbits;
assign  context_out= ExceptionEnable ? econtext_out : (PE ?(enableTaskSwitch? tscontext_out:pcontext_out) : rcontext_out );
assign  address= ExceptionEnable ? econtext_addr : ( PE ?(enableTaskSwitch?tsaddress: paddress) : raddress );
assign  size= PE ?(enableTaskSwitch?tssize: psize ): rsize;

assign  nextIns= PE ? pnextIns : rnextIns;

//Multiplexing ALU signals
assign  cwIn= PE ? pcwIn : rcwIn;
assign  swIn= PE ? pswIn : rswIn;
assign  twIn= PE ? ptwIn : rtwIn;
assign  lipIn= PE ? plipIn : rlipIn;
assign  ldpIn= PE ? pldpIn : rldpIn;
assign  lopIn= PE ? plopIn : rlopIn;
assign  enableintalu = PE ? penableintalu : renableintalu;
assign  enablemmxalu = PE ? penablemmxalu : renablemmxalu;
assign  enablefpualu = PE ? penablefpualu : renablefpualu;
assign  enablessealu = PE ? penablessealu : renablessealu;
assign  enablesse2alu = PE ? penablesse2alu : renablesse2alu;
assign  enablesse3alu = PE ? penablesse3alu : renablesse3alu;
assign  Op1_Tag= PE ? pOp1_Tag : rOp1_Tag;
assign  Op2_Tag= PE ? pOp2_Tag : rOp2_Tag;
assign  in1= PE ? pin1 : rin1;
assign  in2= PE ? pin2 : rin2;
assign  in3= PE ? pin3 : rin3;
assign  infp1= PE ? pinfp1 : rinfp1;
assign  infp2= PE ? pinfp2 : rinfp2;
assign  inm1= PE ? pinm1 : rinm1;
assign  inm2= PE ? pinm2 : rinm2;
assign  insse1_1= PE ? pinsse1_1 : rinsse1_1;
assign  insse1_2= PE ? pinsse1_2 : rinsse1_2;
assign  insse1_3= PE ? pinsse1_3 : rinsse1_3;
assign  insse2_1= PE ? pinsse2_1 : rinsse2_1;
assign  insse2_2= PE ? pinsse2_2 : rinsse2_2;
assign  insse2_3= PE ? pinsse2_3 : rinsse2_3;
assign  insse3_1= PE ? pinsse3_1 : rinsse3_1;
assign  insse3_2= PE ? pinsse3_2 : rinsse3_2;
assign  insse3_3= PE ? pinsse3_3 : rinsse3_3;
assign  newOperation=  rnewOperation;

//Multiplexing memory signals
assign  memAddr = ExceptionEnable ? (ememEnable ? ememAddr:32'bz) : (PE ?(enableTaskSwitch? tsmemAddr: pmemAddr) : rmemAddr);
assign  Rw= ExceptionEnable ? ememRw : ( PE ?(enableTaskSwitch? tsmemRw : pRw ): rRw );
assign  memEnable = ExceptionEnable ?  ememEnable : (PE ? (enableTaskSwitch? tsmemEnable:pmemEnable) : rmemEnable);

assign  memData =ExceptionEnable? (ememRw ? ememData :32'bz) : (PE? (enableTaskSwitch? (tsmemRw ?tsmemData:32'bz): (pRw ? pmemData : 32'bz)):(rRw ? rmemData : 32'bz));


assign  pmemData = pRw ? 32'bz : memData ;
assign  rmemData = rRw ? 32'bz : memData ;
assign  ememData = (ExceptionEnable & !Rw) ? memData : 32'bz;

//Multiplexing exception signals
assign eVect = PE ?(enableTaskSwitch? tsVect: pVect ) : rVect ;
assign ExceptionEnable =  PE ?  (enableTaskSwitch? tsExceptionEnable: pExceptionEnable)  :  rExceptionEnable ;

assign newPC = ExceptionEnable ? eoutPC : (enableintalu ? alunewPC : (PE ? pnewPC : rnewPC));

assign flush = ExceptionEnable ? ePCflush : (enableintalu? aluflush :(PE ? pflush : rflush)) ;

// Multiplexing result from  different alu's
assign result = operation[10] ? (operation[9] ? (operation[8] ? (operation[7] ? 256'bz : outsse3) : (operation[7] ? outsse2 : outsse1)) : (operation[8] ? (operation[7] ? 256'bz : 256'bz) : (operation[7] ? {96'b0,outfp} : {128'b0,outm}))) : {192'b0,out};

assign eflags_out = enableTaskSwitch ? tseflags_out : (enablefpualu ? eflags_outfpu : eflags_outint);


Alu alu_int(enableintalu,operation,in1,in2,in3,eflags_in,opSize[1:0],adSize,out,eflags_outint,aluflush,oldPC,alunewPC);  // INT ALU is being instantiated

mmxAlu alu_mmx(enablemmxalu,operation,inm1,inm2,outm);   // MMX ALU

fpuAlu alu_fpu(enablefpualu,newOperation,infp1,infp2,Op1_Tag,Op2_Tag,swIn,cwIn,lipIn,ldpIn,twIn,opSize,eflags_in,outfp[79:0],outfp[159:80],StatWordOut,eflags_outfpu,CntrlWordOut,LastInsPtrOut,LastDatPtrOut,LastOpCodeOut,TagWordOut);        // FPU ALU

ssealu ssealu(enablessealu,operation,insse1_1,insse1_2,insse1_3,outsse1);//SSE ALU


sse2alu alu_sse2(enablesse2alu,operation,outsse2,insse2_1,insse2_2,insse2_3,MxcsrIn,MxcsrOut);  //SSE2 ALU


sse3Alu alu_sse3(enablesse3alu,operation,outsse3,insse3_1,insse3_2,insse3_3); //SSE3 ALU


//Instantiating exceptionHandler module
exceptionImpl exception(clk,reset,PE,eflags_in,eflags_exception,oldPC,eVect,ePCflush,ExceptionEnable,ExceptionAck,context_in,econtext_addr,emode,op_size,eoutPC,outEIPsize,econtext_out,ememData,ememAddr,ememEnable,ack,ememRw,eenableTS,eTSSsegsel);

//Instantiating Task Switch module
TaskSwitch tsmod(clk,reset,enableTaskSwitch,ack,DesSel,context_in,oldPC,eflags_in,operation,ExceptionAck,tscontext_out,tsaddress,tsflush,tsnewPC,tssize,tsmemData,tsmemAddr,tsmemRw,tsmemEnable,tsmode,tsExceptionEnable,tsVect,tseflags_out,TaskSwitchOver);

//Control Unit core for Real mode
conRealUnit conreal(rmode,roPbits,rcontext_out,rnextIns,raddress,clk,reset,ready,op1,op2,op1Type,op2Type,opSize,adSize,operation,context_in,rsize,oldPC,StatWordIn,StatWordOut,CntrlWordIn,CntrlWordOut,TagWordIn,TagWordOut,LastInsPtrIn,LastDatPtrIn,LastOpCodeIn_Context,LastOpCodeIn_Decoder,LastInsPtrOut,LastDatPtrOut,LastOpCodeOut,rmemData,rmemAddr,rRw,rmemEnable,ack,reflags_out,eflags_in,result,renableintalu,renablemmxalu,renablefpualu,renablessealu,renablesse2alu,renablesse3alu,rcwIn,rswIn,rtwIn,rlipIn,rldpIn,rlopIn,rOp1_Tag,rOp2_Tag,rin1,rin2,rin3,rinfp1,rinfp2,rinm1,rinm2,rinsse1_1,rinsse1_2,rinsse1_3,rinsse2_1,rinsse2_2,rinsse2_3,rinsse3_1,rinsse3_2,rinsse3_3,rnewOperation,PE,rExceptionEnable,rVect,ExceptionAck,rnewPC,rflush);

//Control Unit core for Protected mode
conProUnit conpro(pmode,poPbits,pcontext_out,pnextIns,paddress,clk,reset,ready,op1,op2,op1Type,op2Type,opSize,adSize,operation,context_in,psize,oldPC,StatWordIn,StatWordOut,CntrlWordIn,CntrlWordOut,TagWordIn,TagWordOut,LastInsPtrIn,LastDatPtrIn,LastOpCodeIn_Context,LastOpCodeIn_Decoder,LastInsPtrOut,LastDatPtrOut,LastOpCodeOut,pmemData,pmemAddr,pRw,pmemEnable,ack,eflags_in,result,penableintalu,penablemmxalu,penablefpualu,penablessealu,penablesse2alu,penablesse3alu,pcwIn,pswIn,ptwIn,plipIn,pldpIn,plopIn,pOp1_Tag,pOp2_Tag,pin1,pin2,pin3,pinfp1,pinfp2,pinm1,pinm2,pinsse1_1,pinsse1_2,pinsse1_3,pinsse2_1,pinsse2_2,pinsse2_3,pinsse3_1,pinsse3_2,pinsse3_3,PE,pExceptionEnable,pVect,ExceptionAck,pnewPC,pflush,penableTaskSwitch,pDesSel,TaskSwitchOver,MMUcmd);

endmodule