www.pudn.com > x86.rar > cla32Bit.v, change:2007-12-05,size:3667b


module cla32Bit ( sum, carriesOut, op1, op2, cIn); 
input [31:0]  op1, op2;            	 // 32 bit inputs 
input         cIn;            		 // carry in bit 
output [31:0] sum;             		// 32 bit output sum 
// For intermediatae signals 
wire [7:1]    C;             		// intermediate carry bits 
wire [7:0]    G;            		// intermediate generate group bit for the 4 bit adders 
wire [7:0]    P;            		// intermediate propagate group bit for the 4 bit adders 
//wire [1:0]    G16; 
//wire [1:0]    P16;   the generate and propagate group bit for the 16 bit adders 
output [32:1] carriesOut; 
    
	//instantiantions 2 16 bit CLA adders 
   // first 16 bits 
    
	Adder4Bit CLA1 ( sum[3:0],   carriesOut[4:1], G[0], P[0], op1[3:0],   op2[3:0],   cIn); 
   Adder4Bit CLA2 ( sum[7:4],   carriesOut[8:5], G[1], P[1], op1[7:4],   op2[7:4],   carriesOut[4]); 
   Adder4Bit CLA3 ( sum[11:8],  carriesOut[12:9], G[2], P[2], op1[11:8],  op2[11:8],  carriesOut[8]); 
   Adder4Bit CLA4 ( sum[15:12], carriesOut[16:13], G[3], P[3], op1[15:12], op2[15:12], carriesOut[12]); 
 
 
   // next 16 bits 
   Adder4Bit CLA5 ( sum[19:16],  carriesOut[20:17], G[4], P[4], op1[19:16], op2[19:16], carriesOut[16]); 
   Adder4Bit CLA6 ( sum[23:20],  carriesOut[24:21], G[5], P[5], op1[23:20], op2[23:20], carriesOut[20]); 
   Adder4Bit CLA7 ( sum[27:24],  carriesOut[28:25], G[6], P[6], op1[27:24], op2[27:24], carriesOut[24]); 
   Adder4Bit CLA8 ( sum[31:28],  carriesOut[32:29], G[7], P[7],  op1[31:28], op2[31:28], carriesOut[28]); 
 
endmodule // adder32 
 
// 4 bit CLA adder 
 
module Adder4Bit (	sum, Couts, Generate, Propagate, op1, op2, cIn); 
input [3:0] op1, op2;		// Two 4 Bit numbers to be added 
input       cIn;		//  Input Carry  
output [3:0] sum;	 	// sum of the two 4 Bit Numbers 
output Generate;		 // Generate bit of first 4 Bit CLA adder 
output Propagate;		// Propagate bit of first 4 Bit CLA adder 
//  Temporary wires 
wire [3:0] 	G;	 	  //  Generate bit for each bit 
wire [3:0] 	P;	   	// Propagate bit for each bit 
output [4:1]Couts; 
Adder1Bit Adder0( sum[0], G[0], P[0], op1[0], op2[0], cIn);  // bit 0 
Adder1Bit Adder1( sum[1], G[1], P[1], op1[1], op2[1], Couts[1]); // bit 1 
Adder1Bit Adder2( sum[2], G[2], P[2], op1[2], op2[2], Couts[2]); // bit 2 
Adder1Bit Adder3( sum[3], G[3], P[3], op1[3], op2[3], Couts[3]); // bit 3 
Add4Bits add4Bits( Couts[4], Generate, Propagate, Couts[3:1], G, P, cIn); // C[4] is the Final carry 
endmodule // adder4 
 
 
module Add4Bits( Cout, Generate, Propagate, C, G, P, cIn); 
input  [3:0] G, P;		              // inputs to add together 
input        cIn;		              // carry in bit 
output [3:1] C;		// carry bits to the adders in CLA 
output       Generate;          // generate group signal 
output       Propagate;	       // propagate group signal 
output       Cout;	          	// carry out bit 
// Intermediate Signals 
assign C[1] = G[0] | (P[0] & cIn); 
assign C[2] = G[1] | (P[1] & C[1]); 
assign C[3] = G[2] | (P[2] & C[2]); 
assign Cout = G[3] | (P[3] & C[3]); 
assign Propagate = P[0] & P[1] & P[2] & P[3] ; 
assign Generate  = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & cIn); 
endmodule  
 
 
// One Bit Adder 
 
module Adder1Bit ( sum, Generate, Propagate, op1, op2, cIn); 
input  op1, op2;			     // Two One bit numbers 
input  cIn;			     // The Carry in bit  
output sum;			     // sum of two one bit numbers 
output Generate;			// Generate signal 
output Propagate ;	 // Propagate signal 
assign Propagate = op1^op2; 
assign Generate  = op1 & op2; // Equal to Carry Out 
assign sum       = Propagate ^ cIn; 
endmodule