www.pudn.com > x86.rar > XMM_Registers.v, change:2007-12-05,size:11005b


 
`define XMM0_ON 0 
`define XMM1_ON 1 
`define XMM2_ON 2 
`define XMM3_ON 3 
`define XMM4_ON 4 
`define XMM5_ON 5 
`define XMM6_ON 6 
`define XMM7_ON 7 
 
 
module XMM_Registers(clk,reset,opsize,reg1_enable,reg2_enable,data_in_line,data_out_line); 
 
parameter DATA_SIZE = 255; 
parameter ZERO = 0; 
parameter REG_SIZE = 127; 
 
input  [DATA_SIZE:ZERO] data_in_line; 
output [DATA_SIZE:ZERO] data_out_line; 
 
input [5:0]  opsize; 
 
input clk; 
input reset; 
 
wire	[REG_SIZE:ZERO] XMM0_out; 
wire	[REG_SIZE:ZERO] XMM0_in ; 
wire	[REG_SIZE:ZERO] XMM1_out; 
wire	[REG_SIZE:ZERO] XMM1_in ; 
wire	[REG_SIZE:ZERO] XMM2_out; 
wire	[REG_SIZE:ZERO] XMM2_in ; 
wire	[REG_SIZE:ZERO] XMM3_out; 
wire	[REG_SIZE:ZERO] XMM3_in ; 
wire	[REG_SIZE:ZERO] XMM4_out; 
wire	[REG_SIZE:ZERO] XMM4_in ; 
wire	[REG_SIZE:ZERO] XMM5_out; 
wire	[REG_SIZE:ZERO] XMM5_in ; 
wire	[REG_SIZE:ZERO] XMM6_out; 
wire	[REG_SIZE:ZERO] XMM6_in ; 
wire	[REG_SIZE:ZERO] XMM7_out; 
wire	[REG_SIZE:ZERO] XMM7_in ; 
 
wire    [REG_SIZE:ZERO] reg1_data ; 
wire    [REG_SIZE:ZERO] reg2_data ; 
 
wire XMM0_read,XMM0_read1,XMM0_read2,XMM0_write,XMM0_write1,XMM0_write2; 
wire XMM1_read,XMM1_read1,XMM1_read2,XMM1_write,XMM1_write1,XMM1_write2; 
wire XMM2_read,XMM2_read1,XMM2_read2,XMM2_write,XMM2_write1,XMM2_write2; 
wire XMM3_read,XMM3_read1,XMM3_read2,XMM3_write,XMM3_write1,XMM3_write2; 
wire XMM4_read,XMM4_read1,XMM4_read2,XMM4_write,XMM4_write1,XMM4_write2; 
wire XMM5_read,XMM5_read1,XMM5_read2,XMM5_write,XMM5_write1,XMM5_write2; 
wire XMM6_read,XMM6_read1,XMM6_read2,XMM6_write,XMM6_write1,XMM6_write2; 
wire XMM7_read,XMM7_read1,XMM7_read2,XMM7_write,XMM7_write1,XMM7_write2; 
 
input [4:0] reg1_enable; 
input [4:0] reg2_enable; 
 
wire [1:0] XMM0_size,XMM0_size1,XMM0_size2; 
wire [1:0] XMM1_size,XMM1_size1,XMM1_size2; 
wire [1:0] XMM2_size,XMM2_size1,XMM2_size2; 
wire [1:0] XMM3_size,XMM3_size1,XMM3_size2; 
wire [1:0] XMM4_size,XMM4_size1,XMM4_size2; 
wire [1:0] XMM5_size,XMM5_size1,XMM5_size2; 
wire [1:0] XMM6_size,XMM6_size1,XMM6_size2; 
wire [1:0] XMM7_size,XMM7_size1,XMM7_size2; 
 
 
reg [7:0] reg1Select; 
reg [7:0] reg2Select; 
 
 
always @(reg1_enable ) 
begin 
 
 
case (reg1_enable[2:0]) 
3'b000 : reg1Select = 8'b0000_0001; 
3'b001 : reg1Select = 8'b0000_0010; 
3'b010 : reg1Select = 8'b0000_0100; 
3'b011 : reg1Select = 8'b0000_1000; 
3'b100 : reg1Select = 8'b0001_0000; 
3'b101 : reg1Select = 8'b0010_0000; 
3'b110 : reg1Select = 8'b0100_0000; 
3'b111 : reg1Select = 8'b1000_0000; 
default :reg1Select = 8'b0000_0000; 
endcase 
end 
 
always @(reg2_enable) 
begin 
 
case (reg2_enable[2:0]) 
3'b000 : reg2Select = 8'b0000_0001; 
3'b001 : reg2Select = 8'b0000_0010; 
3'b010 : reg2Select = 8'b0000_0100; 
3'b011 : reg2Select = 8'b0000_1000; 
3'b100 : reg2Select = 8'b0001_0000; 
3'b101 : reg2Select = 8'b0010_0000; 
3'b110 : reg2Select = 8'b0100_0000; 
3'b111 : reg2Select = 8'b1000_0000; 
default :reg2Select = 8'b0000_0000; 
endcase 
end 
 
 
 
// assigning READ signal for register. 
 
//XMM0 
assign XMM0_read1 = reg1Select[0] ? reg1_enable[4]:1'b0; 
assign XMM0_read2 = reg2Select[0] ? reg2_enable[4]:1'b0; 
assign XMM0_read  = XMM0_read1 | XMM0_read2; 
 
//XMM1 
assign XMM1_read1 = reg1Select[1] ? reg1_enable[4]:1'b0; 
assign XMM1_read2 = reg2Select[1] ? reg2_enable[4]:1'b0; 
assign XMM1_read  = XMM1_read1 | XMM1_read2; 
 
//XMM2 
assign XMM2_read1 = reg1Select[2] ? reg1_enable[4]:1'b0; 
assign XMM2_read2 = reg2Select[2] ? reg2_enable[4]:1'b0; 
assign XMM2_read  = XMM2_read1 | XMM2_read2; 
 
//XMM3 
assign XMM3_read1 = reg1Select[3] ? reg1_enable[4]:1'b0; 
assign XMM3_read2 = reg2Select[3] ? reg2_enable[4]:1'b0; 
assign XMM3_read  = XMM3_read1 | XMM3_read2; 
 
//XMM4 
assign XMM4_read1 = reg1Select[4] ? reg1_enable[4]:1'b0; 
assign XMM4_read2 = reg2Select[4] ? reg2_enable[4]:1'b0; 
assign XMM4_read  = XMM4_read1 | XMM4_read2; 
 
//XMM5 
assign XMM5_read1 = reg1Select[5] ? reg1_enable[4]:1'b0; 
assign XMM5_read2 = reg2Select[5] ? reg2_enable[4]:1'b0; 
assign XMM5_read  = XMM5_read1 | XMM5_read2; 
 
//XMM6 
assign XMM6_read1 = reg1Select[6] ? reg1_enable[4]:1'b0; 
assign XMM6_read2 = reg2Select[6] ? reg2_enable[4]:1'b0; 
assign XMM6_read  = XMM6_read1 | XMM6_read2; 
 
//XMM7 
assign XMM7_read1 = reg1Select[7] ? reg1_enable[4]:1'b0; 
assign XMM7_read2 = reg2Select[7] ? reg2_enable[4]:1'b0; 
assign XMM7_read  = XMM7_read1 | XMM7_read2; 
 
 
// writng into registers.. 
 
//XMM0 
assign XMM0_write1 = reg1Select[0] ? reg1_enable[3] : 1'b0; 
assign XMM0_write2 = reg2Select[0] ? reg2_enable[3] : 1'b0; 
assign XMM0_write  = XMM0_write1 | XMM0_write2; 
 
//XMM1 
assign XMM1_write1 = reg1Select[1] ? reg1_enable[3] : 1'b0; 
assign XMM1_write2 = reg2Select[1] ? reg2_enable[3] : 1'b0; 
assign XMM1_write  = XMM1_write1 | XMM1_write2; 
 
//XMM2 
assign XMM2_write1 = reg1Select[2] ? reg1_enable[3] : 1'b0; 
assign XMM2_write2 = reg2Select[2] ? reg2_enable[3] : 1'b0; 
assign XMM2_write  = XMM2_write1 | XMM2_write2; 
 
//XMM3 
assign XMM3_write1 = reg1Select[3] ? reg1_enable[3] : 1'b0; 
assign XMM3_write2 = reg2Select[3] ? reg2_enable[3] : 1'b0; 
assign XMM3_write  = XMM3_write1 | XMM3_write2; 
 
//XMM4 
assign XMM4_write1 = reg1Select[4] ? reg1_enable[3] : 1'b0; 
assign XMM4_write2 = reg2Select[4] ? reg2_enable[3] : 1'b0; 
assign XMM4_write  = XMM4_write1 | XMM4_write2; 
 
//XMM5 
assign XMM5_write1 = reg1Select[5] ? reg1_enable[3] : 1'b0; 
assign XMM5_write2 = reg2Select[5] ? reg2_enable[3] : 1'b0; 
assign XMM5_write  = XMM5_write1 | XMM5_write2; 
 
//XMM6 
assign XMM6_write1 = reg1Select[6] ? reg1_enable[3] : 1'b0; 
assign XMM6_write2 = reg2Select[6] ? reg2_enable[3] : 1'b0; 
assign XMM6_write  = XMM6_write1 | XMM6_write2; 
 
//XMM7 
assign XMM7_write1 = reg1Select[7] ? reg1_enable[3] : 1'b0; 
assign XMM7_write2 = reg2Select[7] ? reg2_enable[3] : 1'b0; 
assign XMM7_write  = XMM7_write1 | XMM7_write2; 
 
 
// assigning size 32 or 64 or 128 
 
//XMM0 
assign XMM0_size1 = reg1Select[0] ? opsize[1:0] : 2'b10; 
assign XMM0_size2 = reg2Select[0] ? opsize[4:3] : 2'b10; 
assign XMM0_size  = reg1Select[0] ?(XMM0_size1):(reg2Select[0]?(XMM0_size2):(2'b10)); 
 
//XMM1 
assign XMM1_size1 = reg1Select[1] ? opsize[1:0] : 2'b10; 
assign XMM1_size2 = reg2Select[1] ? opsize[4:3] : 2'b10; 
assign XMM1_size  = reg1Select[1] ?(XMM1_size1):(reg2Select[1]?(XMM1_size2):(2'b10)); 
 
//XMM2 
assign XMM2_size1 = reg1Select[2] ? opsize[1:0] : 2'b10; 
assign XMM2_size2 = reg2Select[2] ? opsize[4:3] : 2'b10; 
assign XMM2_size  = reg1Select[2] ?(XMM2_size1):(reg2Select[2]?(XMM2_size2):(2'b10)); 
 
//XMM3 
assign XMM3_size1 = reg1Select[3] ? opsize[1:0] : 2'b10; 
assign XMM3_size2 = reg2Select[3] ? opsize[4:3] : 2'b10; 
assign XMM3_size  = reg1Select[3] ?(XMM3_size1):(reg2Select[3]?(XMM3_size2):(2'b10)); 
 
//XMM4 
assign XMM4_size1 = reg1Select[4] ? opsize[1:0] : 2'b10; 
assign XMM4_size2 = reg2Select[4] ? opsize[4:3] : 2'b10; 
assign XMM4_size  = reg1Select[4] ?(XMM4_size1):(reg2Select[4]?(XMM4_size2):(2'b10)); 
 
//XMM5 
assign XMM5_size1 = reg1Select[5] ? opsize[1:0] : 2'b10; 
assign XMM5_size2 = reg2Select[5] ? opsize[4:3] : 2'b10; 
assign XMM5_size  = reg1Select[5] ?(XMM5_size1):(reg2Select[5]?(XMM5_size2):(2'b10)); 
 
//XMM6 
assign XMM6_size1 = reg1Select[6] ? opsize[1:0] : 2'b10; 
assign XMM6_size2 = reg2Select[6] ? opsize[4:3] : 2'b10; 
assign XMM6_size  = reg1Select[6] ?(XMM6_size1):(reg2Select[6]?(XMM6_size2):(2'b10)); 
 
//XMM7 
assign XMM7_size1 = reg1Select[7] ? opsize[1:0] : 2'b10; 
assign XMM7_size2 = reg2Select[7] ? opsize[4:3] : 2'b10; 
assign XMM7_size  = reg1Select[7] ?(XMM7_size1):(reg2Select[7]?(XMM7_size2):(2'b10)); 
 
 
//data_in_line bus assignment 
assign XMM0_in =(reg1Select[0]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[0]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM1_in =(reg1Select[1]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[1]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM2_in =(reg1Select[2]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[2]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM3_in =(reg1Select[3]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[3]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM4_in =(reg1Select[4]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[4]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM5_in =(reg1Select[5]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[5]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM6_in =(reg1Select[6]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[6]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
assign XMM7_in =(reg1Select[7]®1_enable[3]) ?(data_in_line[127:0]) : ((reg2Select[7]®2_enable[3]) ? (data_in_line[255:128]):(256'bz)); 
 
 
assign reg1_data = reg1Select[0] ? XMM0_out : (reg1Select[1] ? XMM1_out : (reg1Select[2] ? XMM2_out :(reg1Select[3] ? XMM3_out :(reg1Select[4]? XMM4_out : (reg1Select[5] ? XMM5_out : (reg1Select[6] ? XMM6_out :(reg1Select[7] ? XMM7_out : 128'bz))))))); 
 
assign reg2_data = reg2Select[0] ? XMM0_out : (reg2Select[1] ? XMM1_out : (reg2Select[2] ? XMM2_out :(reg2Select[3] ? XMM3_out :(reg2Select[4]? XMM4_out : (reg2Select[5] ? XMM5_out : (reg2Select[6] ? XMM6_out :(reg2Select[7] ? XMM7_out : 128'bz))))))); 
 
 
//data_out_line bus assignment 
assign data_out_line[127:0]   = reg1_enable[4]?(reg1_data):80'bz; 
assign data_out_line[255:128] = reg2_enable[4]?(reg2_data):80'bz; 
 
 
Register_XMM XMM0 (.clk(clk),.read(XMM0_read),.write(XMM0_write),.reset(reset),.enable(reg1Select[`XMM0_ON] || reg2Select[`XMM0_ON]),.opsize(XMM0_size),.data_in(XMM0_in),.data_out(XMM0_out)); 
 
Register_XMM XMM1 (.clk(clk),.read(XMM1_read),.write(XMM1_write),.reset(reset),.enable(reg1Select[`XMM1_ON] || reg2Select[`XMM1_ON]),.opsize(XMM1_size),.data_in(XMM1_in),.data_out(XMM1_out)); 
 
Register_XMM XMM2 (.clk(clk),.read(XMM2_read),.write(XMM2_write),.reset(reset),.enable(reg1Select[`XMM2_ON] || reg2Select[`XMM2_ON]),.opsize(XMM2_size),.data_in(XMM2_in),.data_out(XMM2_out)); 
 
Register_XMM XMM3 (.clk(clk),.read(XMM3_read),.write(XMM3_write),.reset(reset),.enable(reg1Select[`XMM3_ON] || reg2Select[`XMM3_ON]),.opsize(XMM3_size),.data_in(XMM3_in),.data_out(XMM3_out)); 
 
Register_XMM XMM4 (.clk(clk),.read(XMM4_read),.write(XMM4_write),.reset(reset),.enable(reg1Select[`XMM4_ON] || reg2Select[`XMM4_ON]),.opsize(XMM4_size),.data_in(XMM4_in),.data_out(XMM4_out)); 
 
Register_XMM XMM5 (.clk(clk),.read(XMM5_read),.write(XMM5_write),.reset(reset),.enable(reg1Select[`XMM5_ON] || reg2Select[`XMM5_ON]),.opsize(XMM5_size),.data_in(XMM5_in),.data_out(XMM5_out)); 
 
Register_XMM XMM6 (.clk(clk),.read(XMM6_read),.write(XMM6_write),.reset(reset),.enable(reg1Select[`XMM6_ON] || reg2Select[`XMM6_ON]),.opsize(XMM6_size),.data_in(XMM6_in),.data_out(XMM6_out)); 
 
Register_XMM XMM7 (.clk(clk),.read(XMM7_read),.write(XMM7_write),.reset(reset),.enable(reg1Select[`XMM7_ON] || reg2Select[`XMM7_ON]),.opsize(XMM7_size),.data_in(XMM7_in),.data_out(XMM7_out)); 
 
endmodule