www.pudn.com > 860bsp.rar > romInit.s
/* romInit.s - 860SAR ROM initialization module */
/* Copyright beijing xinwei shenzhen department,Inc. */
.data
.globl copyright_wind_river
.long copyright_wind_river
/*
modification history
--------------------
*April,4th,2001, an original source be written relying wind river Inc
*ÒÅÁôÎÊÌ⣺1¡¢³ÌÐòͨ¹ýʲô½«¿ªÊ¼¶¨Î»ÔÚ0X100´¦Ö´ÐеÄ
2¡¢¶ÑÕ»µÄ¾ßÌåλÖÃ
3¡¢Î´µ÷ÊÔ
4¡¢Íê³Éʱ¼ £ºApri l 5h£¬2001
*/
/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.
The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart()
*/
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
/* internals */
.globl _romInit /* start of system code */
.globl romInit /* start of system code */
/* externals */
.extern romStart /* system initialization routine */
.text
.align 2
/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
* (
* int startType /@ only used by 2nd entry point @/
* )
*/
/*³ÌÐò¿ªÊ¼Ö´ÐУ¬0x100´¦*/
/*Èç¹ûÊÇÀäÆô¶¯£¬³ÌÐò´Ó0x100´¦¿ªÊ¼£¬ÈÈÆô¶¯´ÓEEPROMµÄ_start´¦¿ªÊ¼*/
_romInit:
romInit:
bl cold /* jump to the cold boot initialization */
bl start /* jump to the warm boot initialization */
/* copyright notice appears at beginning of ROM (in TEXT segment) */
.ascii "Copyright 2001 beijing xinwei shenzhen department, Inc."
.align 2
cold:
li r3, BOOT_COLD /* set cold boot as start type */
/*
* When the PowerPC 860 is powered on, the processor fletch the
* instructions located at the address 0x100. We need to jump
* from the address 0x100 to the EEPROM space.
*/
lis r4, HIADJ(start) /* load r4 with the address */
addi r4, r4, LO(start) /* of start */
lis r5, HIADJ(romInit) /* load r5 with the address */
addi r5, r5, LO(romInit) /* of romInit() */
lis r6, HIADJ(ROM_TEXT_ADRS) /* load r6 with the address */
addi r6, r6, LO(ROM_TEXT_ADRS) /* of ROM_TEXT_ADRS */
sub r4, r4, r5 /* */
add r4, r4, r6
mtspr LR, r4 /* save destination address*/
/* into LR register */
blr /* jump to flash mem address */
start:
/* set the MSR register to a known state */
xor r4, r4, r4 /* clear register R4 */
mtmsr r4 /* cleat the MSR register */
/* DER - clear the Debug Enable Register */
mtspr DER, r4
/* ICR - clear the Interrupt Cause Register */
mtspr ICR, r4
/*
* ICTRL - initialize the Intstruction Support Control register
*
*/
lis r5, HIADJ(0x00000007)
addi r5, r5, LO(0x00000007)
mtspr ICTRL, r5
/* disable the instruction/data cache */
lis r4, HIADJ (CACHE_CMD_DISABLE) /* load disable cmd */
addi r4, r4, LO (CACHE_CMD_DISABLE)
mtspr IC_CST, r4 /* disable I cache */
mtspr DC_CST, r4 /* disable D cache */
/* unlock the instruction/data cache */
lis r4, HIADJ ( CACHE_CMD_UNLOCK_ALL) /* load unlock cmd */
addi r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
mtspr IC_CST, r4 /* unlock all I cache lines */
mtspr DC_CST, r4 /* unlock all D cache lines */
/* invalidate the instruction/data cache */
lis r4, HIADJ (CACHE_CMD_INVALIDATE) /* load invalidate cmd*/
addi r4, r4, LO (CACHE_CMD_INVALIDATE)
mtspr IC_CST, r4 /* invalidate all I cache lines */
mtspr DC_CST, r4 /* invalidate all D cache lines */
/*CACHEµÄºê¶¨ÒåÔÚ"\h\arch\ppc\cachePpcLib.h"ÖÐ*/
/*
* initialize the IMMR register before any non-core registers
* modification.
*/
lis r4, HIADJ(INTERNAL_MEM_MAP_ADDR)
addi r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
mtspr IMMR, r4 /* initialize the IMMR register */
mfspr r4, IMMR /* read it back, to be sure */
rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
/*ÒÔÉÏΪͨÓõIJÙ×÷£¬ÎÞÐë¸Ä¶¯£¬INTERNAL_MEM_MAP_ADffDR=000/00
*ºê¶¨ÒåÔÚ"bsc860.h"ÎļþÖж¨Òå*/
/* SYPCR - turn off the system protection stuff
*/
lis r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
addi r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
stw r5, SYPCR(0)(r4)
/*SYPCR¼Ä´æÆ÷µÄÖµ,Èí¼þ¿´ÃŹ·*/
/*ÏÂÃæÊÇSDRAMµÄ³õʼ»¯ÒÔ¼°Ê±ÖӵĶ¨Òå*/
/* set the SIUMCR register for important debug port, etc... stuff */
lis r6, HIADJ( SIUMCR_FRC| SIUMCR_DLK | SIUMCR_GB5E|SIUMCR_DBGC|\
SIUMCR_DPC| SIUMCR_MLRC_IRQ4)
addi r6, r6, LO(SIUMCR_FRC| SIUMCR_DLK | SIUMCR_GB5E|SIUMCR_DBGC|\
SIUMCR_DPC|SIUMCR_MLRC_IRQ4)
lwz r5, SIUMCR(0)(r4)
or r5, r5, r6
stw r5, SIUMCR(0)(r4)
/*ÉèÖÃSIUMCR*/
/* TBSCR - initialize the Time Base Status and Control register */
lis r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
addi r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
sth r5, TBSCR(0)(r4)
/* set PIT status and control init value */
lis r5,HIADJ( PISCR_PS | PISCR_PITF ) /* 0x00000082 */
addi r5,r5,LO( PISCR_PS | PISCR_PITF ) /* 0x00000082 */
sth r5, PISCR(0)(r4)
/*ÖÜÆÚ¶¨Ê±Æ÷¹Ø±Õ*/
/* set the SPLL frequency */
lis r5, HIADJ(SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT |PLPRCR_TEXPS)
addi r5, r5, LO(SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT |PLPRCR_TEXPS)
stw r5, PLPRCR(0)(r4)
/*ϵͳʱÖÓ50M*/
mptprInit:
/* program the MPTPR */
lis r6, HIADJ(0x0400)
addi r6, r6, LO(0x0400)
sth r6, MPTPR(0)(r4)
/*
* initialize MxMR but don't enable refresh until after
* SDRAM initialization.
*/
lis r5, HIADJ (0xC0104111)
addi r5, r5,LO (0xC0104111)
stw r5, MAMR(0)(r4)
/*
* load r6/r7 with the start/end address of the UPM table for an
* SDRAM @ 50MHZ.
*/
lis r6, HIADJ( upmbTableSdram)
addi r6, r6, LO(upmbTableSdram)
lis r7, HIADJ( upmbTableSdramEnd)
addi r7, r7, LO(upmbTableSdramEnd)
/* init UPMA for memory access */
sub r5, r7, r6 /* compute table size */
srawi r5, r5, 2 /* in integer size */
/* convert UpmTable to ROM based addressing */
lis r7, HIADJ(romInit)
addi r7, r7, LO(romInit)
lis r8, HIADJ(ROM_TEXT_ADRS)
addi r8, r8, LO(ROM_TEXT_ADRS)
sub r6, r6, r7 /* subtract romInit base address */
add r6, r6, r8 /* add in ROM_TEXT_ADRS address */
lis r9, HIADJ(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS1)
addi r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS1)
UpmbWriteLoop:
/* write the UPM table in the UPM */
lwz r10, 0(r6) /* get data from table */
stw r10, MDR(0)(r4) /* store the data to MD register */
stw r9, MCR(0)(r4) /* issue command to MCR register */
addi r6, r6, 4 /* next entry in the table */
addi r9, r9, 1 /* next MAD address */
addi r5,r5,-1
cmpwi r5,0
bne UpmbWriteLoop
/*
* Issue precharge command (PRCG) and wait the precharge time (t-rp).
* Run precharge pattern from UPMB location 5.
*/
lis r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x5)
addi r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x5)
stw r5, MCR(0)(r4)
/* run refresh pattern 8 times */
lis r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_8X | 0x30)
addi r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_8X | 0x30)
stw r5, MCR(0)(r4)
/*
* Configure the 32 bit address to be output on the address bus
* if AMX = 0xb11.
* See section 16.6.4.1 "Arm Words". The following values must
* be placed on the defined SDRAM address pins:
* A[9] = 0 burst write mode
* A[6:4] = 010 cas latency of two
* A[3] = 0 sequential mode
* A[2:0] = 010 burst length 4
*
* The address must be shifted left by 2 bits for 32 bit wide SDRAM...
* (0b0100010 << 2) = 0x88
*/
lis r5, HIADJ(LOCAL_MEM_LOCAL_ADRS | 0x88)
addi r5, r5, LO(LOCAL_MEM_LOCAL_ADRS | 0x88)
stw r5, MAR(0)(r4)
/*
* issue a mode register set (MRS) to initialize the SDRAM mode
* register. This programs the burst length, CAS latency and
* write mode. Run MRS pattern from UPMB location 6.
*/
lis r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x6)
addi r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x6)
stw r5, MCR(0)(r4)
/* enable SDRAM refresh cycles */
lis r5, HIADJ (0xC0904111)
addi r5, r5,LO (0xC0904111)
stw r5, MAMR(0)(r4)
/*ÒÔÏÂÊÇ´æ´¢Æ÷µÄ¶¨Òå*/
/* Map the bank 0 to the EEPROM area */
lis r5, HIADJ(BOOTROM_BASE_ADRS |BR_PS_8| BR_V)
addi r5, r5, LO(BOOTROM_BASE_ADRS|BR_PS_8| BR_V)
stw r5, BR0(0)(r4)
/*CS0µÄ¶¨Ò壬ROM_BASE_ADRSÔÚ"config.h"ÖÐ*/
lis r5, HIADJ( 0xfff80000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK|OR_TRLX)
addi r5, r5, LO(0xfff80000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK|OR_TRLX)
stw r5, OR0(0)(r4)
/*CS0µÄ¶¨Ò壬ROM_BASE_ADRSÔÚ"config.h"ÖÐ,512K=FFF8*/
/*
* Map the bank 1 to SDRAM on borad
*/
lis r5, HIADJ(0xfe000000|OR_CSNT_SAM)
addi r5, r5, LO(0xfe000000|OR_CSNT_SAM)
stw r5, OR1(0)(r4)
lis r5,HIADJ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK)|BR_PS_32|BR_MS_UPMA|BR_V)
addi r5, r5, LO((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK)|BR_PS_32|BR_MS_UPMA|BR_V)
stw r5, BR1(0)(r4)
/*CS1µÄ¶¨Òå*/
/*
* Map the bank 2 to FLASH on borad
*/
lis r5, HIADJ(0xff800000| OR_BI | OR_SCY_5_CLK )
addi r5, r5, LO(0xff800000| OR_BI | OR_SCY_5_CLK )
stw r5, OR2(0)(r4)
lis r5, HIADJ(0x30000000|BR_PS_16|BR_V)
addi r5, r5, LO(0x30000000|BR_PS_16|BR_V)
stw r5, BR2(0)(r4)
/*CS2µÄ¶¨Òå*/
/*
* Map the bank 3 to CPLD on borad, 16bits port
*/
lis r5, HIADJ(0xff800000|OR_CSNT_SAM |OR_BI|OR_SCY_3_CLK|OR_TRLX)
addi r5, r5, LO(0xff800000|OR_CSNT_SAM |OR_BI|OR_SCY_3_CLK|OR_TRLX)
stw r5, OR3(0)(r4)
lis r5, HIADJ(0x04000000|BR_PS_32|BR_V)
addi r5, r5, LO(0x04000000|BR_PS_32|BR_V)
stw r5, BR3(0)(r4)
/*CS3µÄ¶¨Òå*/
/*
* Map the bank 4 to other boards
*/
lis r5, HIADJ(0xfff80000|OR_CSNT_SAM|OR_SCY_6_CLK|OR_ACS_DIV4 ) /* OR_SCY_6_CLK modify from 5 to 6, 05/01/14 */
addi r5, r5, LO(0xfff80000|OR_CSNT_SAM|OR_SCY_6_CLK|OR_ACS_DIV4 )
stw r5, OR4(0)(r4)
lis r5, HIADJ(0x05000000|BR_PS_16|BR_V)
addi r5, r5, LO(0x05000000|BR_PS_16|BR_V)
stw r5, BR4(0)(r4)
/*CS4µÄ¶¨Òå*/
/*
* Map the bank 5 to 512K NVSRAM
*/
lis r5, HIADJ(0xfff80000|OR_BI|OR_SCY_2_CLK)
addi r5, r5, LO(0xfff80000|OR_BI|OR_SCY_2_CLK)
stw r5, OR5(0)(r4)
lis r5, HIADJ(0x06000000|BR_PS_8|BR_V)
addi r5, r5, LO(0x06000000|BR_PS_8|BR_V)
stw r5, BR5(0)(r4)
/*CS5µÄ¶¨Òå*/
/*
* Map the bank 6 to dual_port ram on board
*/
lis r5, HIADJ(0xffff8000|OR_CSNT_SAM | OR_SCY_3_CLK|OR_ACS_DIV4)
addi r5, r5, LO(0xffff8000|OR_CSNT_SAM | OR_SCY_3_CLK|OR_ACS_DIV4)
stw r5, OR6(0)(r4)
lis r5, HIADJ(0x06a00000|BR_PS_16|BR_V)
addi r5, r5, LO(0x06a00000|BR_PS_16|BR_V)
stw r5, BR6(0)(r4)
/*CS6µÄ¶¨Òå*/
/*
* Map the bank 7 to other handware on board
*/
lis r5, HIADJ(0xff000000| OR_SCY_15_CLK |OR_ACS_DIV4)
addi r5, r5, LO(0xff000000|OR_SCY_15_CLK |OR_ACS_DIV4)
stw r5, OR7(0)(r4)
lis r5, HIADJ(0x07000000|BR_PS_16|BR_V)
addi r5, r5, LO(0x07000000|BR_PS_16|BR_V)
stw r5, BR7(0)(r4)
/*CS7µÄ¶¨Òå*/
/* initialize the stack pointer*/
lis sp, HIADJ(STACK_ADRS)
addi sp, sp, LO(STACK_ADRS)
/* go to C entry point */
addi sp, sp, -FRAMEBASESZ /* get frame stack */
/*
* calculate C entry point: routine - entry point + ROM base
* routine = romStart
* entry point = romInit = R7
* ROM base = ROM_TEXT_ADRS = R8
* C entry point: romStart - R7 + R8
*/
lis r6, HIADJ(romStart)
addi r6, r6, LO(romStart) /* load R6 with C entry point */
sub r6, r6, r7 /* routine - entry point */
add r6, r6, r8 /* + ROM base */
mtlr r6 /* move C entry point to LR */
blr /* jump to the C entry point */
/* This 50 MHz SDRAM table is for...
* use HY57V1291620 product of HYDUAN
*/
upmbTableSdram:
/* single read (offset 0x00 in upm ram) */
.long 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00
.long 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
/* burst read (offset 0x08 in upm ram) */
.long 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
.long 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* single write (offset 0x18 in upm ram) */
.long 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* burst write (offset 0x20 in upm ram) */
.long 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
.long 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* refresh (offset 0x30 in upm ram) */
.long 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
/* exception (offset 0x3C in upm ram) */
.long 0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04
upmbTableSdramEnd: