www.pudn.com > art_v46.zip > 240_mb31g_02.ear

#$Id: //depot/sw/branches/ART_V45/bringup/ar5k/config/240_mb31g_02.ear#1 $ 
# EAR config file 
# 
# For chipset: Venice_derby2.1 or freedom_derby2.1. 
# 
# 
# Columns 
#  
# 1 : Select [0=Register Header, 1=Register Data, 2=Version Mask, 3 = VersionId] 
# Rest of columns depend on cfg select setting and register type setting 
#     RegHead | Type0 Write | Type1 Write | Type2 Write | Type3 Write |   
# 2 : Type    | Tag         | Num         | Last        | Last        | 
# 3 : Mode    | Address     | Address     | Analog Bank | OpCode      | 
# 4 : Stage   | Data        | Data        | Column      | Bit Descrip | 
# 5 : Channel | Data (opt)  | Data        | Bit Descrip | Address     | 
# 6 : Disabler|             | Data (opt)  | Data        | Data        | 
# 7 : PLL     |             | Data (opt)  | Data (opt)  | Data (opt)  | 
# 8 :         |             | Data (opt)  | Data (opt)  |             | 
# 9 :         |             | Data (opt)  | Data (opt)  |             | 
#10 :         |             | Data (opt)  | Data (opt)  |             | 
#11 :         |             | Data (opt)  | Data (opt)  |             | 
# 
# Version ID in Header  
3  0xea0e  
 
# First Version Mask  
2  0x4000 
 
# Reg Header Type=3 Mode=11B, 11G and 11g-turbo  
0 3 0x7 1 0 0 0  
1 1 0 3:2 0xa204 0x2  
 
# Reg Header Type=3 Mode=11B, 11G   
0 3 0x3 1 0 0 0  
1 1 0 17:12 0x9858 0x0  
 
# Reg Header Type=3 Mode=ALL MODES  
0 3 0x1ff 1 0 0 0  
1 1 0 21:17 0xa214 0xc  
 
# Reg Header Type=2 Mode=ALL MODES  
0 2 0x1ff 0 0 0 0  
1 0 6  0 253:253 0x1   
1 0 6  2 251:245 0x7f   
1 0 6  2 252:252 0x0 
1 0 6  2 91:90   0x1 
1 0 6  2 93:92   0x2 
1 0 6  2 95:94   0x1 
1 0 6  2 254:254 0x1 
1 1 6  3 146:146 0x1   
 
# Reg Header Type=2 Mode=11a, 11a-turbo  
0 2 0x50 0 0 0 0  
1 1 7  0 38:37 0x3