www.pudn.com > hpbios.rar > ACPI_CT.INC
; []==========================================================[] ; ; This source code is classified as confidential and ; contains trade secrets owned by Award Software, Inc. ; ; Copyright 1984, 1997 ; Award Software, Inc. ; All rights reserved. ; ; []==========================================================[] ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;OEM02 04/19/00 CEC Support S4 wake-up by OS/Scheduled Tasks. ;OEM01 03/27/00 RAX Remove S4BIOS support. ;R00 01/03/00 RIC Initialization. ;---------------------------------------------------------------------------- ;R01 01/11/00 ADS Fixed that PC99 test fail. ;FACP definition for the VIA south chip ; PMIOBase EQU ACPI_Port ;596 PM IO base value programmed in INT_MODEL EQU 0 ;Interrupt mode of ACPI description. SCI_INT EQU 09 ;System pin the SCI interrupt is wired to. SCI_EN EQU 1 ;Enable ACPI SCI PM1a_EVT_BLK EQU PMIOBase+0 ;IO of PM status register PM1b_EVT_BLK EQU 0 ;IO of PM status register PM1a_CNT_BLK EQU PMIOBase+4 ;IO of PM control register PM1b_CNT_BLK EQU 0 ;IO of PM control register PM2_CNT_BLK EQU 0 ;IO of PM control register PM_TMR_BLK EQU PMIOBase+08h ;IO of PM timer register GPE0_BLK EQU PMIOBase+20h ;IO of general purpose register GPE1_BLK EQU 0 ;IO of general purpose register PM1_EVT_LEN EQU 4 ;No. of byte of PM1?_EVT_BLK. PM1_CNT_LEN EQU 2 ;No. of byte of PM1?_CNT_BLK. PM2_CNT_LEN EQU 0 ;No. of byte of PM2_CNT_BLK. PM_TM_LEN EQU 4 ;No. of byte of PM_TMR_BLK. GPE0_BLK_LEN EQU 4 ;No. of byte of GPE0_BLK GPE1_BLK_LEN EQU 0 ;No. of byte of GPE1_BLK GPE1_BASE EQU 0 ; P_LVL2_LAT EQU 90 ;Worst case HW latency in microsec. to enter/exit C2 P_LVL3_LAT EQU 900 ;Worst case HW latency in microsec. to enter/exit C3 FLUSH_SIZE EQU 0 ; FLUSH_STRIDE EQU 0 ; DUTY_OFFSET EQU 0 ; Offset in P_CLK register of CPU duty cycle setting DUTY_WIDTH EQU 1 ; Width of CPU duty cycle bits in P_CLK register. ;OEM01 S4BIOS_F EQU 01h ; S4BIOS_F EQU 0h ;;OEM01 Timer_32bit EQU 100h ; ACPI_Port_Mid EQU ACPI_Port+80h ; END_IO2_Start EQU (ACPI_Port+100h) ; answer NT5.0 that can be used END_IO2_End EQU (ACPI_Port+0FFFH) ; device IO. Hi_END_IO2_Len EQU 0FFFFh-END_IO2_Start IFDEF SMBus_Port END_IO3_Start EQU (SMBus_Port+010h) END_IO3_End EQU (SMBus_Port+0FFFH) Hi_END_IO3_Len EQU 0FFFFh-END_IO3_Start ENDIF; SMBus_Port IFDEF VIA686HM_Port END_IO4_Start EQU (VIA686HM_Port+080h) Hi_END_IO4_Len EQU 0FFFFh-END_IO4_Start ENDIF; VIA686HM_Port ;R01 FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON+RTC_S4+RESET_REG_SUP) ifndef RTC_Wakeup_S4 ;OEM02 FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON+RESET_REG_SUP) ;R01 ;OEM02 - Start else ;RTC_Wakeup_S4 FACPFlag EQU (PROC_C1+WBINVDFlag+SLP_BUTTON+RTC_S4+RESET_REG_SUP) endif ;RTC_Wakeup_S4 ;OEM02 - End Reset_Value EQU 06h ;Reset value Address_Space_Id EQU 1 ;System I/O Register_Bit_Width EQU 8 ;8 bits width Register_Bit_Offset EQU 0 ;bit offset 3 for a full_reset Address_high_Dword EQU 0 ;Up 32bits are zero Address_low_Dword EQU 0cf9h ;Reset control register ifdef Debug_port_table INTERFACE_TYPE EQU 1 ;the type of the registrer interface; subset 16550 interface Base_address_space_ID EQU 1 ;system I/O base_address_bit_width EQU 8 ;8 bits port base_address_bit_offset EQU 0 ;bit offset DEB_port_Base_address EQU 280h DEB_port_High EQU 02h DEB_port_Low EQU 80h endif ;Debug_port_table FACSFlag EQU S4BIOS_F SMI_CMD EQU PMIOBase+02fh ;SMI command port SMI_CMD_RD EQU PMIOBase+02fh ;SMI readm command port S2 EQU 14h ; value for S2 state S3 EQU 04h ; value for S3 state S4 EQU 08h ; value for S4 state DAY_ALRM EQU 7dh ;Index of RTC CMOS day alarm MON_ALRM EQU 7eh ;Index of RTC CMOS month alarm CENTURY_ALRM EQU 32h ;Index of century year high byte GBL_CTL EQU PMIOBase+02ch ;Global Control ;These values are read from SMI_CMD ;by SMI handler to enable/disable ACPI. ACPI_ENABLE EQU 0A1h ;Value assigned by BIOS to check at software ;SMI handler to disable SMI and enable SCI. ACPI_DISABLE EQU 0A0h ;Value to enable SMI ownership ;;;;;debug ifdef S4_Support ;;;;;debug S4BIOS_REQ EQU 0A4h ;Value to enter S4 state (handle by BIOS) ;;;;;debug else; S4_Support S4BIOS_REQ EQU 00h ;Value to enter S4 state (handle by BIOS) ;0= Not support S4 state. ;0a4h= Support S4 sate. ;;;;;debug endif; S4_Support