www.pudn.com > hpbios.rar > 686_UAR1.ASX
//----------------------------------------------------------------------------
//Rev Date Name Description
//----------------------------------------------------------------------------
//R06 09/09/99 JMS Fixed compiler error
//R05 08/02/99 RIC Add "MODEM_RING_ENA_IN_COM1" definition.
//R04 05/11/99 ADS Remove _PRW object
//R03 05/11/99 ADS For HCT 8.1 Convert PnP/APM to ACPI fail
//R02 03/30/99 RIC Fixed that Win98 Device Node report error in disabling
// VIA 686 Superio in BIOS Setup.
//R01 02/04/99 RIC Fix that LPT/COM1/CMO2 can't be disabled in ACPI OS.
//R00 12/02/98 ADS Start of Definitions for VT686 super I/O device
//*************************************************************************//
//* UART1 DEVICE *//
//*************************************************************************//
Device(UAR1) { //UAR1 Device
Name(_HID,EISAID("PNP0501")) //Hardware Device ID
Name(_UID,0x1)
//_ifdef MODEM_RING_ENA_IN_COM1 //R05
//R06 Name(_PRW.Package(2) {0x08,4}) //R05
Name(_PRW,Package(2) {0x08,4}) //R06
//_endif MODEM_RING_ENA_IN_COM1 //R05
Method(_STA,0) { //Status
//R03 If(LNot(\_SB.PCI0.PIB.EP3C)) {
//R03 Return(0x00) // Not present
//R03 } // end if
//R03 start
Store(0x8000[VT686_DEV_FUN0]84, PIND)
Store(PDAT, Local0)
And(Local0, 0x00000100, Local0) // VT686 Function 0 Rx85 bit 0
If(LNot(Local0)) {
Return(0x00)
} //end if
//R03 end
Else {
ENFG() // Enter Config Mode
Store(CRC2, Local0) //Read FSR register
And(Local0, 0x04, Local0) //Read bit2 UART1 enable
If(LNotEqual(Local0, 0x00)){
EXFG()
Return(0x0F) //present, enable, UI, functioning
} // end if
Else {
//Store(CRC7, Local1) // Read FAR1 register
//If (LNotEqual(Local1, 0x00)) {
// EXFG()
// Return(0x0D) //present, disable
//} // end if
Store(CRC7, Local1) // Read SAR1 register //R02 - starts
If (LNotEqual(Local1, 0x00)) {
EXFG()
Return(0x0D) //present, disable
} // end if
else { //R02 - ends
EXFG()
Return(0x00) //present, disable
}
} // end else
} // end else
} // end of _STA method
Method(_DIS,0) { //Disable
//R01 - start
ENFG()
And(CRC2,0xFB,CRC2) // Disable UART1
EXFG()
//R01 - end
} //end _DIS method
Method(_CRS,0) { // Current Serial 1 Resource
Name(BFU1, ResourceTemplate(){
IO(
Decode16,
0x03F8, // Min base I/O addr, UIO1._MIN
0x03F8, // Max base I/O addr, UIO1._MAX
0x08, // Base alignment
0x08, // Number of contig I/O ports
UIO1
)
IRQNoFlags(
UIRQ
)
{0x04} // IRQ 4, UIRQ._INT
} // end Resource Template
) // end buffer BFU1
CreateWordField (BFU1, UIO1._MIN, IMIN) //IO MIN address
CreateWordField (BFU1, UIO1._MAX, IMAX) //IO MAX address
CreateWordField (BFU1, UIRQ._INT, IRQ0) //IRQ Mask
ENFG() // Enter Config Mode
Store(CRC7, Local0) // Read UART1 FSR register
Store(Local0, Local1) // Local1: IOUH, Local0: IOUL
And(Local1, 0x00C0, Local1) // CRC7:
ShiftLeft(Local1, 0x02, Local1) // Bit7-6: ADR9-8
And(Local0, 0x003F, Local0) // Bit5-1: ADR7-3
ShiftLeft(Local0, 0x02, Local0) // Bit0: 0
Or(Local0, Local1, Local0)
Store(Local0, IMIN)
Store(Local0, IMAX)
EXFG() // Exit Config Mode
Store(\_SB.PCI0.PIB.U1IR, Local0) //Get UAR1 IRQ Value
Store(0x01, Local1)
ShiftLeft(Local1, Local0, IRQ0)
Return(BFU1) //Return BFU1
} //end _CRS method
Name(_PRS, ResourceTemplate(){
// First Possible Config 3F8, IRQ 4
StartDependentFnNoPri(){
IO(
Decode16,
0x03F8, // Min base I/O addr
0x03F8, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x04} // IRQ 4
} // end first dependent function
// Second Possible Config 2F8 IRQ 3
StartDependentFnNoPri(){
IO(
Decode16,
0x02F8, // Min base I/O addr
0x02F8, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x03} // IRQ 3
} // end second dependent function
// Third Possible Config 3E8 IRQ 4
StartDependentFnNoPri(){
IO(
Decode16,
0x03E8, // Min base I/O addr
0x03E8, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x04} // IRQ 4
} // end third dependent function
// Fourth Possible Config 2E8 IRQ 3
StartDependentFnNoPri(){
IO(
Decode16,
0x02E8, // Min base I/O addr
0x02E8, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x03} // IRQ 3
} // end fourth dependent function
EndDependentFn() // end dependent functions
} // end Resource Template
) // end _PRS
Method(_SRS,1) { //Set Resource
CreateByteField (Arg0, 0x02, IOLO) //IO Port Low
CreateByteField (Arg0, 0x03, IOHI) //IO Port High
CreateWordField (Arg0, 0x09, IRQ0) // IRQ MASK
ENFG() // Enter Config Mode
Store(CRC2,Local0) // Disable UART1
And(Local0,0xFB,Local1)
Store(Local1,CRC2)
Store(IOLO, Local0) //Set IO
ShiftRight(Local0, 0x02, Local0) //UART1 IO: CRC7
And(Local0, 0xFE, Local0) //Bit7-1 = ADR9-3
Store(IOHI, Local1) //Bit0 = 0
ShiftLeft(Local1, 0x06, Local1)
Or(Local0, Local1, Local0)
Store(Local0, CRC7)
FindSetRightBit(IRQ0, Local0) //Set IRQ
If(LGreater(Local0, 0x00)) {
Decrement(Local0)
}
Store(Local0, \_SB.PCI0.PIB.U1IR)
Store(CRC2,Local0) // Enable UART1
Or(Local0,0x04,Local1)
Store(Local1,CRC2)
EXFG() // Exit Config Mode
} //End of _SRS Method
//R04 Name(_PRW, Package(2) {0x08, 4})
// package (argnum) {GPEbit, wakelevel}
// GP_STS.08,
// lowest sleep state is S4
// no relative power resource
} // end of UART1 device