www.pudn.com > hpbios.rar > 686_LPT.ASL
Device(LPT1) { // LPT Device
Name(PIOM, Buffer(){0x00})
CreateByteField(PIOM, 0x00 ,LPTM) // LPT Mode
Name(_HID, EISAID("PNP0400"))
Method(_STA,0) { // Status
Store(0x80002084, PIND)
Store(PDAT, Local0)
And(Local0, 0x00000100, Local0) // VT686 Function 0 Rx85 bit 0
If(LNot(Local0)) {
Return(0x00)
} //end if
Else { //R02
ENFG() // Enter Config Mode
Store(CRC2, Local0) // Read FSR register
And(Local0, 0x03, Local0) // Bit1-0: PIO Mode
If(LEqual(Local0, 0x01)) { // 01: ECP
EXFG()
Return(0x00) // Not present
} // end if
If(LEqual(Local0, 0x03)) { // 11: PIO Disable
Store(CRC6, Local1) // Read LAR register //R02
If (LNotEqual(Local1, 0x00)) { //R02
EXFG()
Return(0x0D) //present, disable, UI, functioning
} // end if
Else {
EXFG()
Return(0x00) //Not present
} // end else
} // end if
Else {
Store(Local0, LPTM) //Store LPT Mode, Normal, EPP
EXFG()
Return(0x0F) //present, enable, UI, functioning
} // end else
} // end Else //R02
} // end of _STA method
Method(_DIS,0) { // Disable
ENFG()
OR(CRC2,0x03,CRC2) // Disable LPT
EXFG()
} //end _DIS method
Method(_CRS,0) { // Current LPT 1 Resource
Name(BUFL, ResourceTemplate(){
IO(
Decode16,
0x0378, // Min base I/O addr, LIO1._MIN
0x0378, // Max base I/O addr, LIO1._MAX
0x08, // Base alignment, LIO1._ALN
0x08, // Number of contig I/O ports, LIO1._LEN
LIO1
)
IRQNoFlags(
LIRQ
)
{0x07} // IRQ 7, LIRQ._INT
} // end Resource Template
) // end buffer BUFL
CreateWordField(BUFL, LIO1._MIN, IMIN)
CreateWordField(BUFL, LIO1._MAX, IMAX)
CreateByteField(BUFL, LIO1._ALN, LALN)
CreateByteField(BUFL, LIO1._LEN, LLEN) //R05
CreateWordField(BUFL, LIRQ._INT, IRQ0)
ENFG() // Enter Config Mode
Store(CRC6, Local0) // Read CRC6 register
EXFG() // Exit Config Mode
Store(Local0, Local1) // Local1: IOUH, Local0: IOUL
And(Local1, 0xC0, Local1) // CRC6:
ShiftLeft(Local1, 0x02, Local1) // Bit7-6: ADR9-8
ShiftLeft(Local0, 0x02, Local0) // Bit5-0: ADR7-2
Or(Local0, Local1, Local0)
Store(Local0, IMIN)
Store(Local0, IMAX)
If(LEqual(IMIN, 0x03BC)) {
Store(0x04, LALN)
Store(0x04, LLEN)
}
Else {
Store(0x08, LALN)
Store(0x08, LLEN)
}
Store(\_SB.PCI0.PIB.LPIR, Local0) //Get LPT IRQ Value
Store(0x01, Local1)
ShiftLeft(Local1, Local0, IRQ0)
Return(BUFL) //Return BBFL
} //end _CRS method
Name(_PRS, ResourceTemplate(){
StartDependentFnNoPri(){
IO(
Decode16,
0x0378, // Min base I/O addr, LPT1 @ 0x378
0x0378, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x07} // IRQ 7
} // end first dependent function
StartDependentFnNoPri(){
IO(
Decode16,
0x0278, // Min base I/O addr, LPT1 @ 0x278
0x0278, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IRQNoFlags()
{0x05} // IRQ 5
} // end second dependent function
StartDependentFnNoPri(){
IO(
Decode16,
0x03BC, // Min base I/O addr, LPT1 @ 0x3BC
0x03BC, // Max base I/O addr
0x04, // Base alignment
0x04 // Number of contig I/O ports
)
IRQNoFlags()
{0x07} // IRQ 7
} // end third dependent function
EndDependentFn()
} // end of Resource Template
) // end _PRS method
Method(_SRS,1) { //Set Resource
CreateByteField (Arg0, 0x02, IOLO) //IO Port Low
CreateByteField (Arg0, 0x03, IOHI) //IO Port High
CreateWordField (Arg0, 0x09, IRQ0) //IRQ MASK
ENFG() // Enter Config Mode
Store(CRC2, Local0) // Read FSR register
Or(Local0, 0x03, Local0)
Store(Local0, CRC2) // Disable LPT
Store(IOLO, Local0) //Set IO
ShiftRight(Local0, 0x02, Local0) //LPT IO: CRC6
Store(IOHI, Local1) //Bit7-0 = ADR9-2
ShiftLeft(Local1, 0x06, Local1)
Or(Local0, Local1, Local0)
Store(Local0, CRC6)
FindSetRightBit(IRQ0, Local0) //Set IRQ
If(LGreater(Local0, 0x00)) {
Decrement(Local0)
}
Store(Local0, \_SB.PCI0.PIB.LPIR)
Store(CRC2, Local0) // Enable LPT
And(Local0, 0xFC, Local0)
Store(LPTM, Local1)
Or(Local0, Local1, Local1)
Store(Local1, CRC2)
EXFG() // Exit Config Mode
} //End of _SRS Method
} // end of LPT device
Device(ECP1) { //ECP Device
Name (_HID, EISAID("PNP0401")) // PnP ID for ITE8663/8670 ECP Port
Method(_STA,0) { //Status
Store(0x80002084, PIND)
Store(PDAT, Local0)
And(Local0, 0x00000100, Local0) // VT686 Function 0 Rx85 bit 0
If(LNot(Local0)) {
Return(0x00)
} //end if
ENFG() // Enter Config Mode
Store(CRC2, Local0) // Read FSR register
And(Local0, 0x03, Local0) // Bit1-0: PIO Mode
If(LOr(LEqual(Local0, 0x00), LEqual(Local0, 0x02)))
{
EXFG()
Return(0x00) //Not present
} // end if
If(LEqual(Local0, 0x01)) { // 01: ECP
EXFG()
Return(0x0F) //present, enable, UI, functioning
} // end if
If(LEqual(Local0, 0x03)) { // 11: PIO Disable
If(LNotEqual(\_SB.PCI0.PIB.LPDA, 0x00)) {
EXFG()
Return(0x0D) //present, disable, UI, functioning
} // end if
Else {
EXFG()
Return(0x00) //Not present
} // end else
} // end if
} // end of _STA method
Method(_DIS,0) { //Disable
} //end _DIS method
Method(_CRS,0) { // Current ECP Resource
Name(BUFE, ResourceTemplate(){
IO(
Decode16,
0x0378, // Min base I/O addr, EIO1._MIN
0x0378, // Max base I/O addr, EIO1._MAX
0x08, // Base alignment, EIO1._ALN
0x08, // Number of contig I/O ports, EIO1._LEN
EIO1
)
IO(
Decode16,
0x0778, // Min base I/O addr, EIO2._MIN
0x0778, // Max base I/O addr, EIO2._MAX
0x08, // R03
0x08, // R03
EIO2
)
IRQNoFlags(
EIRQ
)
{0x07} // IRQ 7, EIRQ._INT
DMA(
Compatibility,
NotBusMaster,
Transfer8,
EDMA
)
{0x03} // DMA channel 3, EDMA._DMA
} // end Resource Template
) // end buffer BUFE
CreateWordField (BUFE, EIO1._MIN, IMI1) //IO1 MIN address
CreateWordField (BUFE, EIO1._MAX, IMA1) //IO1 MAX address
CreateByteField (BUFE, EIO1._ALN, ALN1) //IO1 Alignment
CreateByteField (BUFE, EIO1._LEN, LEN1) //IO1 Length
CreateWordField (BUFE, EIO2._MIN, IMI2) //IO2 MIN address
CreateWordField (BUFE, EIO2._MAX, IMA2) //IO2 MAX address
CreateByteField (BUFE, EIO2._ALN, ALN2) //R05 IO2 Alignment
CreateByteField (BUFE, EIO2._LEN, LEN2) //R05 IO2 Length
CreateWordField (BUFE, EIRQ._INT, IRQ0) //IRQ
CreateByteField (BUFE, EDMA._DMA, DMA0) //DMA
ENFG() // Enter Config Mode
Store(CRC6, Local0) // Read CRC6 register
EXFG() // Exit Config Mode
Store(Local0, Local1) // Local1: IOUH, Local0: IOUL
And(Local1, 0xC0, Local1) // CRC6:
ShiftLeft(Local1, 0x02, Local1) // Bit7-6: ADR9-8
ShiftLeft(Local0, 0x02, Local0) // Bit5-0: ADR7-2
Or(Local0, Local1, Local0)
Store(Local0, IMI1)
Store(Local0, IMA1)
Add(Local0, 0x400, Local0)
Store(Local0, IMI2)
Store(Local0, IMA2)
If(LEqual(IMI1, 0x03BC)) {
Store(0x04, ALN1)
Store(0x04, LEN1)
Store(0x04, ALN2)
Store(0x04, LEN2)
}
Else {
Store(0x08, ALN1)
Store(0x08, LEN1)
Store(0x04, ALN2)
Store(0x04, LEN2)
}
Store(\_SB.PCI0.PIB.LPIR, Local0) //Get LPT IRQ Value
Store(0x01, Local1)
ShiftLeft(Local1, Local0, IRQ0)
Store(\_SB.PCI0.PIB.LPDA, Local0) //Get LPT DMA Value
And(Local0, 0x03, Local0)
Store(0x01, Local1)
ShiftLeft(Local1, Local0, DMA0)
Return(BUFE) //Return BUFE
} //end _CRS method
Name(_PRS, ResourceTemplate(){
StartDependentFnNoPri(){
IO(
Decode16,
0x0378, // Min base I/O addr, LPT1 @ 0x378
0x0378, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IO(
Decode16,
0x0778, // Min base I/O addr, LPT1 @ 0x378
0x0778, // Max base I/O addr
0x04, // Base alignment
0x04 // Number of contig I/O ports
)
IRQNoFlags()
{0x07} // IRQ7
DMA(
Compatibility,
NotBusMaster,
Transfer8,
)
{0x01, 0x03} // DMA 1, 3
} // end first dependent function
StartDependentFnNoPri(){
IO(
Decode16,
0x0278, // Min base I/O addr, LPT1 @ 0x378
0x0278, // Max base I/O addr
0x08, // Base alignment
0x08 // Number of contig I/O ports
)
IO(
Decode16,
0x0678, // Min base I/O addr, LPT1 @ 0x378
0x0678, // Max base I/O addr
0x04, // Base alignment
0x04 // Number of contig I/O ports
)
IRQNoFlags()
{0x05} // IRQ7
DMA(
Compatibility,
NotBusMaster,
Transfer8,
)
{0x01, 0x03} // DMA 1, 3
} // end second dependent function
EndDependentFn()
} // end of Resource Template
) // end _PRS method
Method(_SRS,1) { //Set Resource
CreateByteField (ARG0, 0x02, IOLO) // IO Port Low
CreateByteField (ARG0, 0x03, IOHI) // IO Port HI
CreateWordField (ARG0, 0x11, IRQ0)
CreateByteField (ARG0, 0x14, DMA0) // DMA Channel to assign
ENFG() // Enter Config Mode
Store(CRC2,Local0) // Read FSR register
Or(Local0, 0x03, Local0)
Store(Local0, CRC2) // Disable LPT
Store(IOLO, Local0) //Set IO
ShiftRight(Local0, 0x02, Local0) //LPT IO: CRC6
Store(IOHI, Local1) //Bit7-0 = ADR9-2
ShiftLeft(Local1, 0x06, Local1)
Or(Local0, Local1, Local0)
Store(Local0, CRC6)
FindSetRightBit(IRQ0, Local0) //Set IRQ
If(LGreater(Local0, 0x00)) {
Decrement(Local0)
}
Store(Local0, \_SB.PCI0.PIB.LPIR)
FindSetRightBit(DMA0, Local0) //Set DMA
If(LGreater(Local0, 0x00)) {
Decrement(Local0)
}
Store(Local0, \_SB.PCI0.PIB.LPDA)
Store(CRC2, Local0) // Enable ECP
And(Local0, 0xFC, Local0)
Or(Local0, 0x01, Local0)
Store(Local0, CRC2)
EXFG() // Exit Config Mode
} //End of _SRS Method
} // end of ECP device