www.pudn.com > SMSC USB2.0.zip > fmc.c
/*============================================================================
____________________________________________________________________________
______________________________________________
SSSS M M CCCC Standard Microsystems Corporation
S MM MM SSSS C Austin Design Center
SSS M M M S C 11000 N. Mopac Expressway
S M M SSS C Stonelake Bldg. 6, Suite 500
SSSS M M S CCCC Austin, Texas 78759
SSSS ______________________________________________
____________________________________________________________________________
Copyright(C) 1999, Standard Microsystems Corporation
All Rights Reserved.
This program code listing is proprietary to SMSC and may not be copied,
distributed, or used without a license to do so. Such license may have
Limited or Restricted Rights. Please refer to the license for further
clarification.
____________________________________________________________________________
Notice: The program contained in this listing is a proprietary trade
secret of SMSC, Hauppauge, New York, and is copyrighted
under the United States Copyright Act of 1976 as an unpublished work,
pursuant to Section 104 and Section 408 of Title XVII of the United
States code. Unauthorized copying, adaption, distribution, use, or
display is prohibited by this law.
____________________________________________________________________________
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph(c)(1)(ii) of the Rights
in Technical Data and Computer Software clause at DFARS 52.227-7013.
Contractor/Manufacturer is Standard Microsystems Corporation,
80 Arkay Drive, Hauppauge, New York, 1178-8847.
____________________________________________________________________________
____________________________________________________________________________
-
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comments tbd
____________________________________________________________________________
Revision History
Date Who Comment
________ ___ _____________________________________________________________
04/20/01 cds initial version
11/27/01 cds moved ram test to the minimos debug code. removed obsolete
fmc_select_none function.
11/28/01 cds added CKCON settings for each device so that access can be
adjusted on a per-device basis.
12/12/01 tbh added the fmc transfer code
02/14/02 tbh clear ramwr_a/b interrupts in fmc_abort_tansfer() to avoid
spurious interrupts after pipe reversal.
02/26/02 tbh added g_fmc_options and intra_burst_callback
03/05/02 ds Moved the Intra_burst callback to after the fmc_wait_count_down_with_timeout fn
added another option to g_fmc_options, to receive 512 bytes is 1.1 speed
03/18/02 tbh moved the intra_burst callback back where it was. the previous
mod caused it to be called at the end of the burst, right before
the end_burst callback. intra_burst must be called -during- the
transfer, not after it.
03/19/02 tbh in fmc_wait_count_down_with_timeout it was receiving and clearing
kbm_sync_fmc_blk, which it shouldnt have.
03/29/02 tbh changed CKCON to 0x02 for CF (to run in pio mode 4)
05/07/02 cds moved intra-burst callback into idata to prevent xdata access during blk_xfer
06/10/02 tbh performance optimizations, added call to fgnd_hpbot_wait_create
from fmc_abort_transfer.
06/20/02 ds Fixed the now rolled-out fmc_wait_blk_irq_with_timeout() in fmc_xfer fn,
to call the end_xfer callback before returning to the caller.
06/20/02 cds added fmc_select_nand() function to select the nand lun
06/21/02 ds The testing for blk_xfer_complete bit in fmc_wait_irq_with_timeout was protected by a
directive, and hence was timing out. Fixed it.
06/26/02 cds added kbm_sync_fmc_irq as a synchronizer that would break
out of the inner fmc_xfer burst loop. ecc errors, or anything
that would cause a nested fmc irq would not break the loop.
07/31/02 cds removed references to g_active_media, and used new media function
media_set_active(...) page in the appropriate media object
from a buffer into variables at 'link-time' defined address.
10/03/02 cds updated the burst loop to break on kbm_isr0_fmc_irq in order to
allow sm/nand devices to correct correctable errors.
10/17/02 cds - project-wide lun data & vtbl paging to reduce code space.
- removed g_active_media from _lun_data, _lun_() virtual functions
- added _lun_data_rd() and _lun_data_wr() macros to bypass lun paging
- added lun_set_active(log_lun) function to switch luns
============================================================================*/
#define __fmc_dot_c__
#include "project.h"
#include "dev.h"
//------------------------------------------------------------------------------
xdata t_result g_fmc_rslt;
xdata uint16 g_fmc_timeout;
xdata uint8 g_fmc_options;
xdata t_udw32 g_start_lb_this_xfer;
xdata t_udw32 g_n_lb_this_xfer;
xdata t_udw32 g_n_lb_this_split;
xdata t_fmc_callback g_fmc_begin_xfer_callback;
xdata t_fmc_callback g_fmc_end_xfer_callback;
xdata t_fmc_callback g_fmc_begin_split_callback;
xdata t_fmc_callback g_fmc_end_split_callback;
xdata t_fmc_callback g_fmc_begin_burst_callback;
// this one cannot be in xdata if using the rev A 210
// because of the MS block bug where rd/wr xdata during
// an fmc xfer corrupts the data.
idata t_fmc_callback g_fmc_intra_burst_callback;
xdata t_fmc_callback g_fmc_end_burst_callback;
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void fmc_dump_registers() reentrant
{
TRACE0(3, fmc, 3, "fmc register dump");
TRACE1(4, fmc, 3, "g_fmc_options: %02x", g_fmc_options);
TRACE1(5, fmc, 3, "g_fmc_timeout: %d", g_fmc_timeout);
TRACE1(6, fmc, 3, " x_fmc_ctl: %02x", x_fmc_ctl);
TRACE1(7, fmc, 3, " x_fmc_mode_ctl: %02x", x_fmc_mode_ctl);
TRACE1(8, fmc, 3, " x_fmc_out_ctl: %02x", x_fmc_out_ctl);
TRACE1(9, fmc, 3, " x_media_sts: %02x", x_media_sts);
TRACE1(10, fmc, 3, " x_crd_ps: %02x", x_crd_ps);
TRACE1(11, fmc, 3, " x_crd_stat: %02x", x_crd_stat);
TRACE1(12, fmc, 3, " x_wu_src1: %02x", x_wu_src1);
TRACE1(13, fmc, 3, " x_wu_msk1: %02x", x_wu_msk1);
TRACE1(14, fmc, 3, " x_crd_stat_msk: %02x", x_crd_stat_msk);
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_dbg_dump_sector()
//
// Declaration:
// void sm_dbg_dump_sector()
//
// Purpose:
//
// Arguments:
//
// Return:
// k_success - on successful completion
//
// Notes:
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
#if 1
void fmc_dbg_dump_sector(uint8* sector) reentrant
{
uint16 i;
i = sector;
_mcu_begin_critical_section();
for (i=0;i<64;i++)
{
trace5(0, n2k, 0, "block[%d]: %04x%04x %04x%04x", (i*8), ( ((uint16*)sector)[i*4]), (((uint16*)sector)[i*4+1]), (((uint16*)sector)[i*4+2]), (((uint16*)sector)[i*4+3]));
}
_mcu_end_critical_section();
}
#endif
//+-----------------------------------------------------------------------------
// Name:
// fmc_select_cfc
//
// Declaration:
// void fmc_select_cfc(void);
//
// Purpose:
// Aim the fmdu at the cfc.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is a FUNCTION, not a DFA.
// Overrides lun_enable_mux.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
void fmc_select_cfc() reentrant
{
#if (k_log_lun_cf < k_max_log_lun)
_mcu_begin_critical_section();
x_fmc_mode_ctl= k_fmc_mode_cfc;
TRACE1(15, fmc, 0, "select cfc device. fmc_mode_ctl:0x%02X", x_fmc_mode_ctl);
// throttle up the CKCON for fastest access to xdata registers
// just dont forget to throttle back to CKCON = 0x02 in ata_register_rd() etc
CKCON = 0x00;
_mcu_end_critical_section();
#endif
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_select_smc
//
// Declaration:
// void fmc_select_smc(void);
//
// Purpose:
// Aim the fmdu at the smc.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is a FUNCTION, not a DFA.
// Overrides lun_enable_mux.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
void fmc_select_smc() reentrant
{
#if (k_log_lun_sm < k_max_log_lun)
_mcu_begin_critical_section();
x_fmc_mode_ctl= k_fmc_mode_smc;
TRACE1(16, fmc, 0, "select smc device. fmc_mode_ctl:0x%02X", x_fmc_mode_ctl);
// slow down access to xdata registers to give hardware time to access the media
CKCON = 0x01;
// set media to the smc structure
media_set_active(k_ix_media_sm) ;
_mcu_end_critical_section();
#endif
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_select_msc
//
// Declaration:
// void fmc_select_msc(void);
//
// Purpose:
// Aim the fmdu at the msc.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is a FUNCTION, not a DFA.
// Overrides lun_enable_mux.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
void fmc_select_msc() reentrant
{
#if (k_log_lun_ms < k_max_log_lun)
_mcu_begin_critical_section();
x_fmc_mode_ctl=k_fmc_mode_msc;
TRACE1(17, fmc, 0, "select msc device. fmc_mode_ctl:0x%02X", x_fmc_mode_ctl);
// throttle up the CKCON for fastest access to xdata registers
//rcc temporarily slow these way down to help screw shings up.
CKCON = 0x00;
// set the media to memory stick
media_set_active(k_ix_media_ms);
_mcu_end_critical_section();
#endif
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_select_sdc
//
// Declaration:
// void fmc_select_sdc(void);
//
// Purpose:
// Aim the fmdu at the sdc.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is a FUNCTION, not a DFA.
// Overrides lun_enable_mux.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
void fmc_select_sdc() reentrant
{
#if (k_log_lun_sd < k_max_log_lun)
_mcu_begin_critical_section();
x_fmc_mode_ctl=k_fmc_mode_sdc;
TRACE1(18, fmc, 0, "select sd/mmc device. fmc_out_ctl:0x%02X fmc_mode_ctl:0x%02X", x_fmc_mode_ctl);
// throttle up the CKCON for fastest access to xdata registers
CKCON = 0x00;
_mcu_end_critical_section();
#endif
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_select_nand
//
// Declaration:
// void fmc_select_nand(void);
//
// Purpose:
// Aim the fmdu at the nand controller (same as the sm controller)
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// - This is a FUNCTION, not a DFA.
// - Overrides lun_enable_mux.
// - This does NOT affect the chip select GPIO
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
void fmc_select_nand() reentrant
{
#if (k_log_lun_nand < k_max_log_lun)
mcu_begin_critical_section();
x_fmc_mode_ctl= k_fmc_mode_smc;
trace1(0, nand, 0, "select nand device. fmc_mode_ctl:0x%02X", x_fmc_mode_ctl);
// slow down access to xdata registers to give hardware time to access the media
CKCON = 0x01;
media_set_active(g_ix_media_nand) ;
mcu_end_critical_section();
#endif
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_abort_transfer
//
// Declaration:
// void fmc_abort_transfer(void);
//
// Purpose:
// Abort the current fmdu transfer.
//
// Arguments:
// None.
//
// Return:
// None.
//
// Notes:
// This is a FUNCTION, not a DFA.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
static void fmc_abort_transfer(void) reentrant;
static void fmc_abort_transfer() reentrant
{
t_udw32 remaining;
TRACE0(19, fmc, 0, "fmc_abort_transfer()");
if (!_dev_sense_vbus())
{
TRACE0(20, fmc, 0, " -- cutting power to the compact flash");
_cf_pwr_off();
//trace0(0, fmc, 0, " -- issuing device reset");
//_dev_soft_reset();
}
_mcu_begin_critical_section();
_mcu_register_clr_bits(x_fmc_ctl, (kbm_fmc_ctl_blk_xfer_en | kbm_fmc_ctl_auto_trans));
_mcu_register_wr(x_isr0, kbm_isr0_ramrd_a |kbm_isr0_ramrd_b |kbm_isr0_ramwr_a |kbm_isr0_ramwr_b);
remaining.u8.hi = _mcu_register_rd(x_fmc_cnt3);
remaining.u8.lh = _mcu_register_rd(x_fmc_cnt2);
remaining.u8.hl = _mcu_register_rd(x_fmc_cnt1);
remaining.u8.lo = _mcu_register_rd(x_fmc_cnt0);
_mscbot_set_residue(remaining.u32);
// if (g_usbrst)
// fgnd_hpbot_wait_create();
_mcu_end_critical_section();
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_wait_count_down_with_timeout
//
// Declaration:
// t_result fmc_wait_count_down_with_timeout(uint16 ticks);
//
// Purpose:
// Wait for the block transfer to edecrement to zero, without yielding.
//
// Arguments:
// ticks - a uint16 representing the timeout limit
//
// Return:
// A t_result indicating:
// k_success - the ata status register logically anded with the mask equals the value.
// k_usbrst - usb reset signalling was detected while waiting.
// k_aborted - traffic occurred on the control pipe while waiting (probably a mass storage reset).
// k_timeout - timeout limit exceeded.
//
// Notes:
// This is a FUNCTION, not a DFA.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
t_result fmc_wait_count_down_with_timeout(uint16 ticks) reentrant
{
t_sync sync;
TRACE0(21, fmc, 1, "fmc_wait_blk_count_down_with_timeout()");
thread_set_timer(ticks);
do
{
sync = thread_got_sync(kbm_sync_abort |kbm_sync_usbrst |kbm_sync_timer);
_thread_clr_sync(sync);
if (sync & kbm_sync_usbrst)
{
TRACE0(22, fmc, 1, "fmc_wait_blk_count_down_with_timeout() - error: kbm_sync_usbrst");
return k_usbreset;
}
if (sync & kbm_sync_abort)
{
TRACE0(23, fmc, 1, "fmc_wait_blk_count_down_with_timeout() - error: kbm_sync_abort");
return k_aborted;
}
if (sync & kbm_sync_timer)
{
TRACE0(24, fmc, 1, "fmc_wait_blk_count_down_with_timeout() - error: timeout awaiting irq");
return k_timeout;
}
//_mcu_begin_critical_section();
//TRACE4(161, fmc, 0, "fmc_cnt#: %02x%02x%02x%02x", x_fmc_cnt3, x_fmc_cnt2, x_fmc_cnt1, x_fmc_cnt0);
//_mcu_end_critical_section();
} while (_mcu_register_rd(x_fmc_cnt3) | _mcu_register_rd(x_fmc_cnt2) |
_mcu_register_rd(x_fmc_cnt1) | _mcu_register_rd(x_fmc_cnt0));
return k_success;
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_wait_blk_irq_with_timeout
//
// Declaration:
// t_result fmc_wait_blk_irq_with_timeout(uint16 ticks);
//
// Purpose:
// Wait for the block transfer interrupt, without yielding.
//
// Arguments:
// ticks - a uint16 representing the timeout limit
//
// Return:
// A t_result indicating:
// k_success - the ata status register logically anded with the mask equals the value.
// k_usbrst - usb reset signalling was detected while waiting.
// k_aborted - traffic occurred on the control pipe while waiting (probably a mass storage reset).
// k_timeout - timeout limit exceeded.
//
// Notes:
// This is a FUNCTION, not a DFA.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
t_result fmc_wait_blk_irq_with_timeout(uint16 ticks) reentrant
{
t_sync sync;
TRACE0(25, fmc, 1, "fmc_wait_blk_irq_with_timeout()");
thread_set_timer(ticks);
do
{
sync = thread_got_sync(kbm_sync_abort |kbm_sync_usbrst |kbm_sync_timer |kbm_sync_fmc_blk);
_thread_clr_sync(sync);
if (sync & kbm_sync_usbrst)
{
TRACE0(26, fmc, 1, "fmc_wait_blk_irq_with_timeout() - error: kbm_sync_usbrst");
return k_usbreset;
}
if (sync & kbm_sync_abort)
{
TRACE0(27, fmc, 1, "fmc_wait_blk_irq_with_timeout() - error: kbm_sync_abort");
return k_aborted;
}
if (sync & kbm_sync_timer)
{
TRACE0(28, fmc, 1, "fmc_wait_blk_irq_with_timeout() - error: timeout awaiting irq");
return k_timeout;
}
#if 1
// AAA: fmc_transfer doesnt call this any more - it unrolls the function
// so i turned this optimization off to avoid breaking sd.
// added this to poll instead of taking the interrupt
if (_mcu_register_rd(x_isr0) & kbm_isr0_blk_xfer_complete)
break;
#endif
} while (!(sync & kbm_sync_fmc_blk));
return k_success;
}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
t_result fmc_dflt_callback() reentrant
{
return k_success;
}
//+-----------------------------------------------------------------------------
// Name:
// fmc_transfer
//
// Declaration:
// t_result fmc_transfer(void);
//
// Purpose:
// Transfer data via the fmdu.
//
// Arguments:
// No parameters, but the caller must have previously called:
// _fmc_set_start_lb_8() OR _fmc_set_start_lb_32()
// AND
// _fmc_set_lb_count_8() Or _fmc_set_lb_count_32()
// AND
// _fmc_set_callback()
// AND
// _fmc_set_timeout()
// AND
// must have set both _lun_data(lun, max_lb_per_split) and _lun_data(lun, max_lb_per_burst)
//
// Return:
// A t_result indicating:
// k_success - transfer complete.
// k_usbrst - usb reset signalling was detected during the transfer.
// k_aborted - traffic occurred on the control pipe during the transfer (probably a mass storage reset).
// k_timeout - timeout limit exceeded.
//
// Notes:
// The class/subclass/protocol specifies starting logical block and the number
// of logical blocks for a read/write/verify operation. A logical block is
// analogous to a disk sector, which is 512 bytes for all of the supported flash
// cards.
//
// A "transfer" is a data move that satisfies the full amount requested via the
// protocol; e.g., read 2500 logical blocks starting from logical block 99.
// However, some drive types cannot move arbitrarily large numbers of logical blocks
// in a single command. For example, ata drives have a single byte sector count
// register and thus can only move 256 sectors (logical blocks) per command.
// Therefore, to read 300 logical blocks from an ata drive requires two read commands;
// one for 256 logical blocks, another for the remainder. Thus the transfer must
// be "split" into multiple peices, and the command issued for each split.
//
// Additionally, different drive types have differnt policies for generating
// interrupts. Some can move multiple logical blocks without generating an interrupt,
// others generate an interrupt after moving each logical block, and others after
// various numbers of logical blocks have moved. Moving some number of logical
// blocks and then getting an interrupt is called a "burst".
//
// These globals affect the operation. Don't access then directly in callbacks.
// Instead, use the _fmc_set_xxxx() and _fmc_get_xxxx() wrappers. That will
// keep the implementation opaque (knock on wood). Use _fmc_get_result to check the result.
//
// g_start_lb_this_xfer - specifies the starting logical block for the transfer
// per the protocol
// g_n_lb_this_xfer - specifies the total number of logical blocks to move
// for this transfer per the protocol
// _lun_data(lun, max_lb_per_split) - specifies the maximum number of logical blocks that the
// drive can handle in a single command
// _lun_data(lun, max_lb_per_burst) - specifies the maximum number of logical blocks that the
// drive can deliver before generating an interrupt
// g_fmc_begin_xfer_callback - specifies the callback function to begin a xfer
// g_fmc_end_xfer_callback - specifies the callback function to end a xfer
// g_fmc_begin_split_callback - specifies the callback function to begin a split;
// i.e., issue the command
// g_fmc_end_split_callback - specifies the callback function to end a split;
// i.e., check for error
// g_fmc_begin_burst_callback - specifies the callback function to begin a burst;
// i.e., check drive ready
// g_fmc_end_burst_callback - specifies the callback function to end a burst;
// i.e., check for error
//
// This is a FUNCTION, not a DFA.
//
// Since:
// fmc-1.0
//------------------------------------------------------------------------------
// oddly enough, moving these to xdata a tiny smidge is faster
// than manipulating them on the stack...
xdata t_udw32 n_lb_this_burst;
xdata t_udw32 n_bytes_this_burst;
xdata uint32 tmp;
t_result fmc_transfer() reentrant
{
// profile:
// ms reads: 76msec avg to 230msec max per 64Kbytes
// ms writes: 145msec to 150msec per 64Kbytes
//if ((g_bot_xfer_dir == k_dir_read)&&
// (g_bot_data_len.u32 > 0xE000)){_profile_on(7);}
TRACE0(29, fmc, 1, "fmc_transfer()");
// do this to get kbm_sync_abort delivered if there is traffic on the control pipe
_isr_bind_dma_owner(g_tid, kbm_sync_none);
// begin the xfer
//_profile_on(4);
g_fmc_rslt = (*g_fmc_begin_xfer_callback)();
//_profile_off(4);
if (k_success != g_fmc_rslt)
goto EXIT;
// need to disable auto transfer?
if (!(g_fmc_options & kbm_fmc_disable_auto_xfer))
{
// enable auto transfer - start receiving data packets
_mcu_register_set_bits(x_fmc_ctl, kbm_fmc_ctl_auto_trans);
TRACE0(30, fmc, 0, "auto-transfer bit on");
}
//------------------------------------------------------------------------------
// moved from inside the burst loop to improve speed of MS transfers
//------------------------------------------------------------------------------
// enable the block transfer hardware
if (sie_is_high_speed())
{
TRACE0(31, fmc, 0, "HS mode set-->kbm_fmc_ctl_512_byte_pkt");
_mcu_register_set_bits(x_fmc_ctl, kbm_fmc_ctl_512_byte_pkt);
}
else
{
TRACE0(32, fmc, 0, "FS mode clr-->kbm_fmc_ctl_512_byte_pkt");
_mcu_register_clr_bits(x_fmc_ctl, kbm_fmc_ctl_512_byte_pkt);
}
// check to see if we need to force the 512 byte xfer irrespective of the speed
if ((g_fmc_options & kbm_fmc_xfer_512_byte_pkt))
{
TRACE0(33, fmc, 0, "option forced set-->kbm_fmc_ctl_512_byte_pkt");
_mcu_register_set_bits(x_fmc_ctl, kbm_fmc_ctl_512_byte_pkt);
}
//------------------------------------------------------------------------------
// process each split in the transaction
//while (g_n_lb_this_xfer.u32)
while (!_u32_equ_0(g_n_lb_this_xfer))
{
_thread_clr_sync(kbm_sync_fmc_irq);
// determine the number of logical blocks for this split
tmp = _lun_data(max_lb_per_split);
if (g_n_lb_this_xfer.u32 > tmp)
{
// split
TRACE0(34, fmc, 0, "fmc_transfer() - multiple splits");
g_n_lb_this_split.u32 = tmp;
}
else
{
// not split, or final split
TRACE0(35, fmc, 0, "fmc_transfer() - single split");
g_n_lb_this_split.u32 = g_n_lb_this_xfer.u32;
}
// begin the split
TRACE2(36, fmc, 0, "n_lb_this_split: %04x%04x" , _hw(g_n_lb_this_split.u32), _lw(g_n_lb_this_split.u32));
//_profile_on(5);
g_fmc_rslt = (*g_fmc_begin_split_callback)();
//_profile_off(5);
if (k_success != g_fmc_rslt)
goto EXIT;
// process each burst in the split
//while (g_n_lb_this_split.u32)
while (!_u32_equ_0(g_n_lb_this_split))
{
// determine the number of logical blocks in this burst
tmp = _lun_data(max_lb_per_burst);
if (g_n_lb_this_split.u32 > tmp)
{
// multi-burst
TRACE0(37, fmc, 0, "fmc_transfer() - multiple bursts");
n_lb_this_burst.u32 = tmp;
}
else
{
// single burst, or final burst
TRACE0(38, fmc, 0, "fmc_transfer() - single burst");
n_lb_this_burst.u32 = g_n_lb_this_split.u32;
}
// determine the number of bytes in this burst
TRACE2(39, fmc, 0, "n_lb_this_burst: %04x%04x", _hw(n_lb_this_burst.u32), _lw(n_lb_this_burst.u32));
#if 1
n_bytes_this_burst.u32 = n_lb_this_burst.u32 * 512L;
#else
// tried to hand multiply by a constant - didnt work right - needs work
n_bytes_this_burst.u8.hi = n_lb_this_burst.u8.lh << 1;
n_bytes_this_burst.u8.lh = n_lb_this_burst.u8.hl << 1;
n_bytes_this_burst.u8.hl = n_lb_this_burst.u8.lo << 1;
n_bytes_this_burst.u8.lo = 0;
#endif
// begin the burst
//_profile_on(6);
g_fmc_rslt = (*g_fmc_begin_burst_callback)();
//_profile_off(6);
if (k_success != g_fmc_rslt)
goto EXIT;
// clear, and unmask, the block xfer interrupt
//irq_control(k_irq_blk_xfer_complete, kbm_irqctl_clear |kbm_irqctl_unmask);
_mcu_register_wr(x_isr0, kbm_isr0_blk_xfer_complete);
// AAA: do not take the interrupt at end of transfer and watch for a synchronizer.
// instead poll for the bit and eliminate the isr entry/exit overhead.
//_mcu_register_clr_bits(x_imr0, kbm_isr0_blk_xfer_complete);
// write the count registers
_mcu_register_wr(x_fmc_cnt3, n_bytes_this_burst.u8.hi);
_mcu_register_wr(x_fmc_cnt2, n_bytes_this_burst.u8.lh);
_mcu_register_wr(x_fmc_cnt1, n_bytes_this_burst.u8.hl);
_mcu_register_wr(x_fmc_cnt0, n_bytes_this_burst.u8.lo);
TRACE4(40, fmc, 0, "fmc_cnt#: %02x%02x%02x%02x", x_fmc_cnt3, x_fmc_cnt2, x_fmc_cnt1, x_fmc_cnt0);
// prime the loop to "resume" transfer, w/o calling split/burst/xfer mechanisms
// to allow luns to fix and/or correct errors in mid transfer, then to continue
// data xfer.
g_fmc_rslt = k_resume;
while (g_fmc_rslt == k_resume)
{
_mcu_register_set_bits(x_fmc_ctl, kbm_fmc_ctl_blk_xfer_en);
TRACE0(41, fmc, 0, "fmdu activated");
// call a xfer-in-progress callback?
//_profile_on(5);
g_fmc_rslt = (*g_fmc_intra_burst_callback)();
//_profile_off(5);
if (k_success != g_fmc_rslt)
goto EXIT;
// !!! possible performance optimization is to make these fctns inline...
// wait for the end of the burst
if (g_fmc_options & kbm_fmc_end_burst_on_count_down)
{
// wait for the count to decrement to zero
g_fmc_rslt = fmc_wait_count_down_with_timeout(g_fmc_timeout);
}
else
{
t_sync sync;
// wait for the block transfer irq
// unrolled: g_fmc_rslt = fmc_wait_blk_irq_with_timeout(g_fmc_timeout);
// poll for bit instead of taking irq and waiting synch.
//_profile_on(7);
//trace0(0, fmc, 1, "fmc_wait_blk_irq_with_timeout()");
thread_set_timer(g_fmc_timeout);
do
{
sync = thread_got_sync(kbm_sync_abort |kbm_sync_usbrst |kbm_sync_timer|kbm_sync_fmc_irq);
_thread_clr_sync(sync);
if (sync & kbm_sync_usbrst)
{
TRACE0(42, fmc, 1, "optimized fmc_wait_blk_irq_with_timeout() - error: kbm_sync_usbrst");
g_fmc_rslt = k_usbreset;
break;
}
if (sync & kbm_sync_abort)
{
TRACE0(43, fmc, 1, "optimized fmc_wait_blk_irq_with_timeout() - error: kbm_sync_abort");
g_fmc_rslt = k_aborted;
break;
}
if (sync & kbm_sync_timer)
{
TRACE0(44, fmc, 1, "optimized fmc_wait_blk_irq_with_timeout() - error: timeout awaiting irq");
g_fmc_rslt = k_timeout;
break;
}
if (sync & kbm_sync_fmc_irq)
{
TRACE0(45, fmc, 1, "optimized fmc_wait_blk_irq_with_timeout() - error: kbm_sync_fmc_irq") ;
// set to success, since we don't know the cause of the error yet... the specific end-burst
// function should determine the actual status fot eh fmc xfer
g_fmc_rslt = k_success;
break;
}
// AAA: added this to poll instead of taking the interrupt
// cds: added isr bit fmc_irq to break out of loop for fmc error (ecc or otherwise) detection
} while (!(_mcu_register_rd(x_isr0) & (kbm_isr0_blk_xfer_complete|kbm_isr0_fmc_irq) ));
//_profile_off(7);
}
if (k_success != g_fmc_rslt)
{
goto EXIT;
}
// end the burst
//_profile_on(6);
g_fmc_rslt = (*g_fmc_end_burst_callback)();
//_profile_off(6);
if (k_resume == g_fmc_rslt)
{
TRACE0(46, fmc, 0, "resuming fmc transfer");
continue;
}
else
if (k_success != g_fmc_rslt)
goto EXIT;
}
// update start block for next split
g_start_lb_this_xfer.u32 += n_lb_this_burst.u32;
// decrement the number of logical blocks remaining in the split
g_n_lb_this_split.u32 -= n_lb_this_burst.u32;
// decrement the number of logical blocks remaining in the transfer
g_n_lb_this_xfer.u32 -= n_lb_this_burst.u32;
// track the mscbot byte residue
_mscbot_decr_residue(n_bytes_this_burst.u32);
}
// end the split
//_profile_on(5);
g_fmc_rslt = (*g_fmc_end_split_callback)();
//_profile_off(5);
if (k_success != g_fmc_rslt)
goto EXIT;
}
EXIT:
// check for an error
if (k_success != g_fmc_rslt)
fmc_abort_transfer();
else
_lun_data(sensep) = &sense_none;
// end the xfer
// ??? need to get the returned result? can end_xfer fail the xfer?
//_profile_on(4);
(*g_fmc_end_xfer_callback)();
//_profile_off(4);
//_profile_off(7);
// exit, stage left
return g_fmc_rslt;
}
//---eof------------------------------------------------------------------------