www.pudn.com > SMSC USB2.0.zip > flash.c
/*============================================================================
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SSSS M M CCCC Standard Microsystems Corporation
S MM MM SSSS C Austin Design Center
SSS M M M S C 11000 N. Mopac Expressway
S M M SSS C Stonelake Bldg. 6, Suite 500
SSSS M M S CCCC Austin, Texas 78759
SSSS ______________________________________________
____________________________________________________________________________
Copyright(C) 1999, Standard Microsystems Corporation
All Rights Reserved.
This program code listing is proprietary to SMSC and may not be copied,
distributed, or used without a license to do so. Such license may have
Limited or Restricted Rights. Please refer to the license for further
clarification.
____________________________________________________________________________
Notice: The program contained in this listing is a proprietary trade
secret of SMSC, Hauppauge, New York, and is copyrighted
under the United States Copyright Act of 1976 as an unpublished work,
pursuant to Section 104 and Section 408 of Title XVII of the United
States code. Unauthorized copying, adaption, distribution, use, or
display is prohibited by this law.
____________________________________________________________________________
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph(c)(1)(ii) of the Rights
in Technical Data and Computer Software clause at DFARS 52.227-7013.
Contractor/Manufacturer is Standard Microsystems Corporation,
80 Arkay Drive, Hauppauge, New York, 1178-8847.
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flash.c -
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comments tbd
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Revision History
Date Who Comment
________ ___ _____________________________________________________________
04/15/02 tbh initial version
08/06/02 tbh ported to fmc, only support k_sst29sf010 because code is so
tight we can barely afford to spare 3 x 128 byte pages.
09/07/02 tbh updated to function correctly. only supports sst39vf010.
09/11/02 tbh reserve block of code for nvdata
============================================================================*/
#include "project.h"
#include "flash.h"
// NOTICE - 09/05/02 - only works with sst39vf010
//------------------------------------------------------------------------------
// IMPORTANT: putting these into xdata depends on linking such that xdata
// falls at 0x4000, which can only be done on the 210, 211, 242 (the ones
// with the extra 12K of ram for map tables etc). If you link these into
// the 0x0400-0x06FF range they will be nailed when flash becomes executable.
xdata t_result g_flash_rslt;
//------------------------------------------------------------------------------
// NOTE:
// All of the functions in this module must be located in code space between
// 0x0400 and 0x06FF so that they can be copied into the 768 byte sram of
// the 201 and executed from there while the flash chip is being erased or
// reprogrammed.
//
// so... link this module so that everything begins at 0x0400 in code space
//------------------------------------------------------------------------------
#ifdef k_opt_otprom
// IMPORTANT: putting these into xdata depends on linking such that xdata
// falls at 0x4000, which can only be done on the 210, 211, 242 (the ones
// with the extra 12K of ram for map tables etc). If you link these into
// the 0x0400-0x06FF range they will be nailed when flash becomes executable.
// for the 210 with a 4K segment flash an entire 4K of ram gets whacked
// reserve these addresses so no xdata variables are stored there
static xdata uint8 _rsrv0 _at_ k_flash_addr0;
static xdata uint8 _rsrv1 _at_ k_flash_addr1;
// reserve these addresses so no code is stored there
static code uint8 _rsrv2[256] _at_ k_nvstore_base;
//------------------------------------------------------------------------------
// Declaration:
// static void otprom_read(uint8 addr);
//
// Purpose:
// Read the flash chip.
//
// Arguments:
// addr - the offset from the base of the 256 nvstore bytes in flash.
//
// Return:
// None.
//
// Note:
// Doesn't need to switch banks because app bank is target
//
// Since:
// atapi-2.0
//------------------------------------------------------------------------------
uint8 otprom_read(uint8 addr) reentrant
{
trace3(0, dfu, 0, "otprom_read(offset:%d) 0x%04X:%02X", addr, k_nvstore_base + addr, CBYTE[k_nvstore_base + addr]);
return CBYTE[k_nvstore_base + addr];
}
//------------------------------------------------------------------------------
// Note:
// Must be relocatable.
// Must be in ram at address 0x0400.
// Must be called from within a critical section.
//------------------------------------------------------------------------------
void otprom_erase_sector(void) reentrant;
void otprom_erase_sector() reentrant
{
XBYTE[k_otprom_base] = k_flash_sector_erase;
// disable dw8051 capability to write code space as if it were xdata
SPCFNC = 0;
// monitor DQ6 toggle bit of the flash chip to
// determine when the sector erase is complete.
// sector erase takes 25 msec per sector on the sst39vf010.
while (1)
{
if (CBYTE[k_otprom_base] == CBYTE[k_otprom_base])
if (CBYTE[k_otprom_base] == CBYTE[k_otprom_base])
if (CBYTE[k_otprom_base] == CBYTE[k_otprom_base])
{
//g_flash_rslt = k_success;
break;
}
}
}
//------------------------------------------------------------------------------
// Note:
// Must be relocatable.
// Must be in ram at address 0x0400.
// Must be called from within a critical section.
//------------------------------------------------------------------------------
static idata uint16 _dst_addr;
static idata uint8 _value;
void otprom_write_byte(void) reentrant;
void otprom_write_byte() reentrant
{
// 4k of data is stashed at k_ram_base in xdata
XBYTE[_dst_addr] = _value;
// disable dw8051 capability to write code space as if it were xdata
SPCFNC = 0;
// monitor DQ6 toggle bit of the flash chip to
// determine when the byte program is complete.
// (takes 20usec on the sst39vf010
g_tmp = 1;
while (g_tmp++)
{
if (CBYTE[_dst_addr] == _value)
if (CBYTE[_dst_addr] == _value)
if (CBYTE[_dst_addr] == _value)
{
break;
}
}
}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void otprom_write_flush() reentrant
{
uint16 i;
uint16 src_addr;
_flash_execute_from_flash();
// copy otprom_erase_sector() into ram
memcpy((uint8 xdata *)(0x0400), (uint8 code *)(otprom_erase_sector), 256);
if (memcmp((uint8 xdata *)(0x0400), (uint8 code *)(otprom_erase_sector), 256))
{
trace0(0, dfu, 0, "ERROR: copy failed.");
mcu_halt();
}
// call it
// erase top sector of flash
// enable dw8051 capability to write code space as if it were xdata
_mcu_begin_critical_section();
SPCFNC = kbm_WRS;
XBYTE[k_flash_addr0] = 0xAA;
XBYTE[k_flash_addr1] = 0x55;
XBYTE[k_flash_addr0] = 0x80;
XBYTE[k_flash_addr0] = 0xAA;
XBYTE[k_flash_addr1] = 0x55;
_flash_execute_from_ram();
((t_code_fragment)0x0400)();
_flash_execute_from_flash();
_mcu_end_critical_section();
// copy otprom_write_byte() into ram
memcpy((uint8 xdata *)(0x0400), (uint8 code *)(otprom_write_byte), 256);
if (memcmp((uint8 xdata *)(0x0400), (uint8 code *)(otprom_write_byte), 256))
{
trace0(0, dfu, 0, "ERROR: copy failed.");
mcu_halt();
}
// copy 4k of ram into flash
_mcu_begin_critical_section();
_dst_addr = k_otprom_base;
src_addr = k_ram_base;
_value = XBYTE[src_addr];
for (i=0; i