www.pudn.com > sn068s.zip > CPUOPS.NI
;%define TRAP_INVALID_JUMP
; 65c816 opcodes 0x00-0x0F:
; 00: BRK s 2,8
; 01: ORA (d,x) 2,6
; 02: COP s 2,8
; 03: ORA d,s 2,4
; 04: TSB d 2,5
; 05: ORA d 2,3
; 06: ASL d 2,5
; 07: ORA [d] 2,6
; 08: PHP s 1,3
; 09: ORA # 2,2
; 0A: ASL A 1,2
; 0B: PHD s 1,4
; 0C: TSB a 3,6
; 0D: ORA a 3,4
; 0E: ASL a 3,6
; 0F: ORA al 4,5
;
; 65c816 opcodes 0x10-0x1F:
; 10: BPL r 2,2
; 11: ORA (d),y 2,5
; 12: ORA (d) 2,5
; 13: ORA (d,s),y 2,7
; 14: TRB d 2,5
; 15: ORA d,x 2,4
; 16: ASL d,x 2,6
; 17: ORA [d],y 2,6
; 18: CLC i 1,2
; 19: ORA a,y 3,4
; 1A: INC A 1,2
; 1B: TCS i 1,2
; 1C: TRB a 3,6
; 1D: ORA a,x 3,4
; 1E: ASL a,x 3,7
; 1F: ORA al,x 4,5
;
; 65c816 opcodes 0x20-0x2F:
; 20: JSR a 3,6
; 21: ORA (d,x) 2,6
; 22: JSL al 4,8
; 23: AND d,s 2,4
; 24: BIT d 2,3
; 25: AND d 2,3
; 26: ROL d 2,5
; 27: AND [d] 2,6
; 28: PLP s 1,4
; 29: AND # 2,2
; 2A: ROL A 1,2
; 2B: PLD s 1,5
; 2C: BIT a 3,4
; 2D: AND a 3,4
; 2E: ROL a 3,6
; 2F: AND al 4,5
;
; 65c816 opcodes 0x30-0x3F:
; 30: BMI r 2,2
; 31: AND (d),y 2,5
; 32: AND (d) 2,5
; 33: AND (d,s),y 2,7
; 34: BIT d,x 2,4
; 35: AND d,x 2,4
; 36: ROL d,x 2,6
; 37: AND [d],y 2,6
; 38: SEC i 1,2
; 39: AND a,y 3,4
; 3A: DEC A 1,2
; 3B: TSC i 1,2
; 3C: BIT a,x 3,4
; 3D: AND a,x 3,4
; 3E: ROL a,x 3,7
; 3F: AND al,x 4,5
;
; 65c816 opcodes 0x40-0x4F:
; 40: RTI s 1,7
; 41: EOR (d,x) 2,6
; 42: WDM 2,2
; 43: EOR d,s 2,4
; 44: MVP xya 3,7
; 45: EOR d 2,3
; 46: LSR d 2,5
; 47: EOR [d] 2,6
; 48: PHA s 1,3
; 49: EOR # 2,2
; 4A: LSR A 1,2
; 4B: PHK s 1,3
; 4C: JMP a 3,3
; 4D: EOR a 3,4
; 4E: LSR a 3,6
; 4F: EOR al 4,5
;
; 65c816 opcodes 0x50-0x5F:
; 50: BVC r 2,2
; 51: EOR (d),y 2,5
; 52: EOR (d) 2,5
; 53: EOR (d,s),y 2,7
; 54: MVN xya 3,7
; 55: EOR d,x 2,4
; 56: LSR d,x 2,6
; 57: EOR [d],y 2,6
; 58: CLI i 1,2
; 59: EOR a,y 3,4
; 5A: PHY s 1,2
; 5B: TCD i 1,2
; 5C: JML al 4,4
; 5D: EOR a,x 3,4
; 5E: LSR a,x 3,7
; 5F: EOR al,x 4,5
;
; 65c816 opcodes 0x60-0x6F:
; 60: RTS s 1,6
; 61: ADC (d,x) 2,6
; 62: PER s 3,6
; 63: ADC d,s 2,4
; 64: STZ d 2,3
; 65: ADC d 2,3
; 66: ROR d 2,5
; 67: ADC [d] 2,6
; 68: PLA s 1,4
; 69: ADC # 2,2
; 6A: ROR A 1,2
; 6B: RTL s 1,6
; 6C: JMP (a) 3,5
; 6D: ADC a 3,4
; 6E: ROR a 3,6
; 6F: ADC al 4,5
;
; 65c816 opcodes 0x70-0x7F:
; 70: BVS r 2,2
; 71: ADC (d),y 2,5
; 72: ADC (d) 2,5
; 73: ADC (d,s),y 2,7
; 74: STZ d,x 2,4
; 75: ADC d,x 2,4
; 76: ROR d,x 2,6
; 77: EOR [d],y 2,6
; 78: SEI i 1,2
; 79: ADC a,y 3,4
; 7A: PLY s 1,4
; 7B: TDC i 1,2
; 7C: JMP (a,x) 3,6
; 7D: ADC a,x 3,4
; 7E: ROR a,x 3,7
; 7F: ADC al,x 4,5
;
; 65c816 opcodes 0x80-0x8F:
; 80: BRA r 2,2
; 81: STA (d,x) 2,6
; 82: BRL rl 3,3
; 83: STA d,s 2,4
; 84: STY d 2,3
; 85: STA d 2,3
; 86: STX d 2,3
; 87: STA [d] 2,6
; 88: DEY i 1,2
; 89: BIT # 2,2
; 8A: TXA i 1,2
; 8B: PHB s 1,3
; 8C: STY a 3,4
; 8D: STA a 3,4
; 8E: STX a 3,4
; 8F: STA al 4,5
;
; 65c816 opcodes 0x90-0x9F:
; 90: BCC r 2,2
; 91: STA (d),y 2,6
; 92: STA (d) 2,5
; 93: STA (d,s),y 2,7
; 94: STY d,x 2,4
; 95: STA d,x 2,4
; 96: STX d,y 2,4
; 97: STA [d],y 2,6
; 98: TYA i 1,2
; 99: STA a,y 3,5
; 9A: TXS i 1,2
; 9B: TXY i 1,2
; 9C: STZ a 3,4
; 9D: STA a,x 3,5
; 9E: STZ a,x 3,5
; 9F: STA al,x 4,5
;
; 65c816 opcodes 0xA0-0xAF:
; A0: LDY # 2,2
; A1: LDA (d,x) 2,6
; A2: LDX # 2,2
; A3: LDA d,s 2,4
; A4: LDY d 2,3
; A5: LDA d 2,3
; A6: LDX d 2,3
; A7: LDA [d] 2,6
; A8: TAY i 1,2
; A9: LDA # 2,2
; AA: TAX i 1,2
; AB: PLB s 1,4
; AC: LDY a 3,4
; AD: LDA a 3,4
; AE: LDX a 3,4
; AF: LDA al 4,5
;
; 65c816 opcodes 0xB0-0xBF:
; B0: BCS r 2,2
; B1: LDA (d),y 2,5
; B2: LDA (d) 2,5
; B3: LDA (d,s),y 2,7
; B4: LDY d,x 2,4
; B5: LDA d,x 2,4
; B6: LDX d,y 2,4
; B7: LDA [d],y 2,6
; B8: CLV i 1,2
; B9: LDA a,y 3,4
; BA: TSX i 1,2
; BB: TYX i 1,2
; BC: LDY a,x 3,4
; BD: LDA a,x 3,4
; BE: LDX a,y 3,4
; BF: LDA al,x 4,5
;
; 65c816 opcodes 0xC0-0xCF:
; C0: CPY # 2,2
; C1: CMP (d,x) 2,6
; C2: REP # 2,3
; C3: CMP d,s 2,4
; C4: CPY d 2,3
; C5: CMP d 2,3
; C6: DEC d 2,5
; C7: CMP [d] 2,6
; C8: INY i 1,2
; C9: CMP # 2,2
; CA: DEX i 1,2
; CB: WAI i 1,3
; CC: CPY a 3,4
; CD: CMP a 3,4
; CE: DEC a 3,6
; CF: CMP al 4,5
;
; 65c816 opcodes 0xD0-0xDF:
; D0: BNE r 2,2
; D1: CMP (d),y 2,5
; D2: CMP (d) 2,5
; D3: CMP (d,s),y 2,7
; D4: PEI s 2,6
; D5: CMP d,x 2,4
; D6: DEC d,x 2,6
; D7: CMP [d],y 2,6
; D8: CLD i 1,2
; D9: CMP a,y 3,4
; DA: PHX s 1,3
; DB: STP i 1,3
; DC: JML (a) 3,6
; DD: CMP a,x 3,4
; DE: DEC a,x 3,7
; DF: CMP al,x 4,5
;
; 65c816 opcodes 0xE0-0xEF:
; E0: CPX # 2,2
; E1: SBC (d,x) 2,6
; E2: SEP # 2,3
; E3: SBC d,s 2,4
; E4: CPX d 2,3
; E5: SBC d 2,3
; E6: INC d 2,5
; E7: SBC [d] 2,6
; E8: INX i 1,2
; E9: SBC # 2,2
; EA: NOP i 1,2
; EB: XBA i 1,3
; EC: CPX a 3,4
; ED: SBC a 3,4
; EE: INC a 3,6
; EF: SBC al 4,5
;
; 65c816 opcodes 0xF0-0xFF:
; F0: BEQ r 2,2
; F1: SBC (d),y 2,5
; F2: SBC (d) 2,5
; F3: SBC (d,s),y 2,7
; F4: PEA s 3,5
; F5: SBC d,x 2,4
; F6: INC d,x 2,6
; F7: SBC [d],y 2,6
; F8: SED i 1,2
; F9: SBC a,y 3,4
; FA: PLX s 1,4
; FB: XCE i 1,2
; FC: JSR (a,x) 3,6
; FD: SBC a,x 3,4
; FE: INC a,x 3,7
; FF: SBC al,x 4,5
;
;%1 = vector, %2 = offset
%macro NativeInterrupt 2
mov al,B_PB
E0_PUSH_B
GET_PC eax
add eax,byte 2
E0_PUSH_W
E0_SETUPFLAGS ; Put flags into true 65c816 format
E0_PUSH_B
mov R_NativePC,%1 ; PC = Native mode vector
mov eax,%2
mov B_PB,byte 0 ; Setup bank
mov B_PBOffset,eax ; Offset of bank 0 ROM
STORE_FLAGS_I 1 ; Disable IRQs
add R_NativePC,eax
mov [CycleTable],byte 4 ; SlowROM bank
STORE_FLAGS_D 0 ; Disable decimal mode
OPCODE_EPILOG
%endmacro
;%1 = vector, %2 = offset
%macro Emu6502Interrupt 2
GET_PC eax
add eax,byte 2
E1_PUSH_W
E1_SETUPFLAGS ; Put flags into true 65c816 format
E1_PUSH_B
mov R_NativePC,%1 ; PC = Native mode vector
mov eax,%2
mov B_PB,byte 0 ; Setup bank
mov B_PBOffset,eax ; Offset of bank 0 ROM
STORE_FLAGS_I 1 ; Disable IRQs
add R_NativePC,eax
mov [CycleTable],byte 4 ; SlowROM bank
STORE_FLAGS_D 0 ; Disable decimal mode
OPCODE_EPILOG
%endmacro
; 00
ALIGNC
EXPORT_C E0_BRK
NativeInterrupt B_BRK_Nvector,B_BRK_Noffset
ALIGNC
EXPORT_C E1_BRK
Emu6502Interrupt B_IRQ_Evector,B_IRQ_Eoffset
; 01
EM_ORA Od_xO,Direct_Indexed_Indirect
E0_ORA Od_xO,Direct_Indexed_Indirect
; 02
ALIGNC
EXPORT_C E0_COP
NativeInterrupt B_COP_Nvector,B_COP_Noffset
ALIGNC
EXPORT_C E1_COP
Emu6502Interrupt B_COP_Evector,B_COP_Eoffset
; 03
EM_ORA d_s,Stack_Relative
E0_ORA d_s,Stack_Relative
; 04
EM_TSB d,Direct
E0_TSB d,Direct
; 05
EM_ORA d,Direct
E0_ORA d,Direct
; 06
EM_ASL d,Direct
E0_ASL d,Direct
; 07
EM_ORA IdI,Direct_Indirect_Long
E0_ORA IdI,Direct_Indirect_Long
; 08
ALIGNC
EXPORT_C E0_PHP
inc R_NativePC
E0_SETUPFLAGS
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHP
inc R_NativePC
E1_SETUPFLAGS
E1_PUSH_B
OPCODE_EPILOG
; 09
EM_ORA i,Immediate
E0_ORA i,Immediate
; 0A
ALIGNC
EXPORT_C EM_SLA
inc R_NativePC
mov al,B_A
add al,al
sbb cl,cl
mov B_A,al
STORE_FLAGS_NZC al,cl
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_SLA
inc R_NativePC
mov eax,B_A
add ax,ax
sbb cl,cl
STORE_FLAGS_N ah
mov B_A,eax
or al,ah
STORE_FLAGS_C cl
STORE_FLAGS_Z al
OPCODE_EPILOG
; 0B
ALIGNC
EXPORT_C E0_PHD
inc R_NativePC
mov eax,B_D
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHD
inc R_NativePC
mov eax,B_D
E1_PUSH_W
OPCODE_EPILOG
; 0C
EM_TSB a,Absolute
E0_TSB a,Absolute
; 0D
EM_ORA a,Absolute
E0_ORA a,Absolute
; 0E
EM_ASL a,Absolute
E0_ASL a,Absolute
; 0F
EM_ORA al,Absolute_Long
E0_ORA al,Absolute_Long
; 10
BFC BPL,SNES_FLAG_N
; 11
EM_ORA OdO_y,Direct_Indirect_Indexed
E0_ORA OdO_y,Direct_Indirect_Indexed
; 12
EM_ORA OdO,Direct_Indirect
E0_ORA OdO,Direct_Indirect
; 13
EM_ORA Od_sO_y,Stack_Relative_Indirect_Indexed
E0_ORA Od_sO_y,Stack_Relative_Indirect_Indexed
; 14
EM_TRB d,Direct
E0_TRB d,Direct
; 15
EM_ORA d_x,Direct_Index_X
E0_ORA d_x,Direct_Index_X
; 16
EM_ASL d_x,Direct_Index_X
E0_ASL d_x,Direct_Index_X
; 17
EM_ORA IdI_y,Direct_Indirect_Indexed_Long
E0_ORA IdI_y,Direct_Indirect_Indexed_Long
; 18
ALIGNC
EXPORT_C ALL_CLC
inc R_NativePC
STORE_FLAGS_C ah
OPCODE_EPILOG
; 19
EM_ORA a_y,Absolute_Index_Y
E0_ORA a_y,Absolute_Index_Y
; 1A
ALIGNC
EXPORT_C EM_INA
mov al,B_A
inc R_NativePC
inc al
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_INA
mov eax,B_A
inc R_NativePC
inc eax
mov B_A,ax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 1B
ALIGNC
EXPORT_C E0_TCS
inc R_NativePC
mov eax,B_A
mov B_S,eax
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_TCS
inc R_NativePC
mov al,B_A
mov B_S,al
OPCODE_EPILOG
; 1C
EM_TRB a,Absolute
E0_TRB a,Absolute
; 1D
EM_ORA a_x,Absolute_Index_X
E0_ORA a_x,Absolute_Index_X
; 1E
EM_ASL a_x,Absolute_Index_X
E0_ASL a_x,Absolute_Index_X
; 1F
EM_ORA al_x,Absolute_Long_Index_X
E0_ORA al_x,Absolute_Long_Index_X
; 20
ALIGNC
EXPORT_C E0_JSR_a
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 2 ; last instruction byte PC in ax
E0_PUSH_W ; Address of last byte not next instruction (huh!)
ADDR_Absolute_JMP
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x20
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
ALIGNC
EXPORT_C E1_JSR_a
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 2 ; last instruction byte PC in ax
E1_PUSH_W ; Address of last byte not next instruction (huh!)
ADDR_Absolute_JMP
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x20
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 21
EM_AND Od_xO,Direct_Indexed_Indirect
E0_AND Od_xO,Direct_Indexed_Indirect
; 22
ALIGNC
EXPORT_C E0_JSL_al ; JSR Absolute long address
mov al,B_PB
E0_PUSH_B ; Push PB
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 3 ; Address of last byte of instruction
E0_PUSH_W ; Push PC
mov al,[1+R_NativePC]
xor ebx,ebx
mov ah,[2+R_NativePC]
mov bl,[3+R_NativePC]
mov B_PB,bl
mov R_NativePC,eax
test [MEMSEL],bl ; Check bus speed against PB
mov al,5
jnz .fastrom
mov al,4
.fastrom:
mov [CycleTable],al ; Update bus speed
mov edi,R_NativePC
shl ebx,16
or edi,ebx
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,ebx
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x22
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
ALIGNC
EXPORT_C E1_JSL_al
mov al,B_PB
E1_PUSH_B ; Push PB
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 3 ; Address of last byte of instruction
E1_PUSH_W ; Push PC
mov al,[1+R_NativePC]
xor ebx,ebx
mov ah,[2+R_NativePC]
mov bl,[3+R_NativePC]
mov B_PB,bl
mov R_NativePC,eax
test [MEMSEL],bl ; Check bus speed against PB
mov al,5
jnz .fastrom
mov al,4
.fastrom:
mov [CycleTable],al ; Update bus speed
mov edi,R_NativePC
shl ebx,16
or edi,ebx
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,ebx
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x22
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 23
EM_AND d_s,Stack_Relative
E0_AND d_s,Stack_Relative
; 24
EM_BIT d,Direct
E0_BIT d,Direct
; 25
EM_AND d,Direct
E0_AND d,Direct
; 26
EM_ROL d,Direct
E0_ROL d,Direct
; 27
EM_AND IdI,Direct_Indirect_Long
E0_AND IdI,Direct_Indirect_Long
; 28
ALIGNC
EXPORT_C E0_PLP
inc R_NativePC
E0_PULL_B
E0_RESTOREFLAGS
JUMP_FLAG SNES_FLAG_I,.no_irq
mov al,[IRQ_pin]
test al,al
jz .no_irq
SAVE_PC ebx
add R_Cycles,byte 60 ; IRQ processing: 2 IO + 6 bank0
call E0_IRQ
LOAD_PC
.no_irq:
SET_TABLE_MX
ALIGNC
EXPORT_C E1_PLP
inc R_NativePC
E1_PULL_B
E1_RESTOREFLAGS
JUMP_FLAG SNES_FLAG_I,CPU_RETURN,near
mov al,[IRQ_pin]
test al,al
jz near CPU_RETURN
SAVE_PC ebx
add R_Cycles,byte 52 ; IRQ processing: 2 IO + 5 bank0
call E1_IRQ
LOAD_PC
OPCODE_EPILOG
; 29
EM_AND i,Immediate
E0_AND i,Immediate
; 2A
ALIGNC
EXPORT_C EM_RLA
mov cl,B_C_flag
mov al,B_A
inc R_NativePC
add cl,255 ;MAKE_CARRY
adc al,al
sbb cl,cl
mov B_A,al
STORE_FLAGS_NZC al,cl
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_RLA
mov cl,B_C_flag
mov eax,B_A
inc R_NativePC
add cl,255 ;MAKE_CARRY
adc ax,ax
sbb cl,cl
STORE_FLAGS_N ah
mov B_A,eax
or al,ah
STORE_FLAGS_C cl
STORE_FLAGS_Z al
OPCODE_EPILOG
; 2B
ALIGNC
EXPORT_C E0_PLD
inc R_NativePC
E0_PULL_W
mov B_D,eax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PLD
inc R_NativePC
E1_PULL_W
mov B_D,eax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 2C
EM_BIT a,Absolute
E0_BIT a,Absolute
; 2D
EM_AND a,Absolute
E0_AND a,Absolute
; 2E
EM_ROL a,Absolute
E0_ROL a,Absolute
; 2F
EM_AND al,Absolute_Long
E0_AND al,Absolute_Long
; 30
BFS BMI,SNES_FLAG_N
; 31
EM_AND OdO_y,Direct_Indirect_Indexed
E0_AND OdO_y,Direct_Indirect_Indexed
; 32
EM_AND OdO,Direct_Indirect
E0_AND OdO,Direct_Indirect
; 33
EM_AND Od_sO_y,Stack_Relative_Indirect_Indexed
E0_AND Od_sO_y,Stack_Relative_Indirect_Indexed
; 34
EM_BIT d_x,Direct_Index_X
E0_BIT d_x,Direct_Index_X
; 35
EM_AND d_x,Direct_Index_X
E0_AND d_x,Direct_Index_X
; 36
EM_ROL d_x,Direct_Index_X
E0_ROL d_x,Direct_Index_X
; 37
EM_AND IdI_y,Direct_Indirect_Indexed_Long
E0_AND IdI_y,Direct_Indirect_Indexed_Long
; 38
ALIGNC
EXPORT_C ALL_SEC ; Set Carry Flag
mov al,1
inc R_NativePC
STORE_FLAGS_C al
OPCODE_EPILOG
; 39
EM_AND a_y,Absolute_Index_Y
E0_AND a_y,Absolute_Index_Y
; 3A
ALIGNC
EXPORT_C EM_DEA
mov al,B_A
inc R_NativePC
dec al
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_DEA
mov eax,B_A
inc R_NativePC
dec eax
mov B_A,ax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 3B
ALIGNC
EXPORT_C ALL_TSC
inc R_NativePC
mov eax,B_S
mov B_A,eax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 3C
EM_BIT a_x,Absolute_Index_X
E0_BIT a_x,Absolute_Index_X
; 3D
EM_AND a_x,Absolute_Index_X
E0_AND a_x,Absolute_Index_X
; 3E
EM_ROL a_x,Absolute_Index_X
E0_ROL a_x,Absolute_Index_X
; 3F
EM_AND al_x,Absolute_Long_Index_X
E0_AND al_x,Absolute_Long_Index_X
; 40
ALIGNC
EXPORT_C E0_RTI
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E0_PULL_B
E0_RESTOREFLAGS
E0_PULL_W
mov R_NativePC,eax
E0_PULL_B
mov B_PB,al
test [MEMSEL],al ; Check bus speed against PB
mov bl,5
jnz .fastrom
mov bl,4
.fastrom:
mov ah,0
mov [CycleTable],bl ; Update bus speed
mov edi,R_NativePC
shl eax,16
or edi,eax
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,eax
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
JUMP_FLAG SNES_FLAG_I,.no_irq
mov al,[IRQ_pin]
test al,al
jz .no_irq
SAVE_PC ebx
add R_Cycles,byte 60 ; IRQ processing: 2 IO + 6 bank0
call E0_IRQ
LOAD_PC
.no_irq:
SET_TABLE_MX
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x40
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp .read_direct ;*
%endif
ALIGNC
EXPORT_C E1_RTI
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E1_PULL_B
E1_RESTOREFLAGS
E1_PULL_W
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
JUMP_FLAG SNES_FLAG_I,CPU_RETURN,near
mov al,[IRQ_pin]
test al,al
jz near CPU_RETURN
SAVE_PC ebx
add R_Cycles,byte 52 ; IRQ processing: 2 IO + 5 bank0
call E1_IRQ
LOAD_PC
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x40
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 41
EM_EOR Od_xO,Direct_Indexed_Indirect
E0_EOR Od_xO,Direct_Indexed_Indirect
; 42
ALIGNC
EXPORT_C ALL_WDM
add R_NativePC,byte 2
OPCODE_EPILOG
; 43
EM_EOR d_s,Stack_Relative
E0_EOR d_s,Stack_Relative
; 44
ALIGNC
EXPORT_C E0_MVP
push ebx ; Cycles per instruction iteration
.again:
mov al,[1+R_NativePC] ; Dest bank
mov bl,[2+R_NativePC] ; Src bank
mov B_DB,al
mov ax,B_X ; Src address
shl ebx,16
add ebx,eax
dec eax
mov B_X,ax
GET_BYTE
mov ebx,B_DB_Shifted
mov bx,B_Y ; Dest address
SET_BYTE
mov eax,B_A
dec ebx
sub eax,byte 1
mov B_Y,bx
jc .done
test R_Cycles,R_Cycles
jge .event
mov B_A,ax
add R_Cycles,[esp]
xor eax,eax
xor ebx,ebx
jmp .again
ALIGNC
.done:
add R_NativePC,byte 3
.event:
mov B_A,ax
pop edi
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_MVP
push ebx ; Cycles per instruction iteration
.again:
mov al,[1+R_NativePC] ; Dest bank
mov bl,[2+R_NativePC] ; Src bank
mov B_DB,al
mov al,B_X ; Src address
shl ebx,16
add ebx,eax
dec eax
mov B_X,al
GET_BYTE
mov ebx,B_DB_Shifted
mov bl,B_Y ; Dest address
SET_BYTE
mov eax,B_A
dec ebx
sub eax,byte 1
mov B_Y,bl
jc .done
test R_Cycles,R_Cycles
jge .event
mov B_A,ax
add R_Cycles,[esp]
xor eax,eax
xor ebx,ebx
jmp short .again
ALIGNC
.done:
add R_NativePC,byte 3
.event:
mov B_A,ax
pop edi
OPCODE_EPILOG
; 45
EM_EOR d,Direct
E0_EOR d,Direct
; 46
EM_LSR d,Direct
E0_LSR d,Direct
; 47
EM_EOR IdI,Direct_Indirect_Long
E0_EOR IdI,Direct_Indirect_Long
; 48
ALIGNC
EXPORT_C E0_PHA
inc R_NativePC
mov eax,B_A
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C EM_PHA
inc R_NativePC
mov eax,B_A
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHA
inc R_NativePC
mov eax,B_A
E1_PUSH_B
OPCODE_EPILOG
; 49
EM_EOR i,Immediate
E0_EOR i,Immediate
; 4A
ALIGNC
EXPORT_C EM_SRA
mov al,B_A
inc R_NativePC
shr al,byte 1
sbb cl,cl
mov B_A,al
STORE_FLAGS_NZC al,cl
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_SRA
mov eax,B_A
inc R_NativePC
shr eax,byte 1
sbb cl,cl
STORE_FLAGS_N ah
mov B_A,eax
or al,ah
STORE_FLAGS_C cl
STORE_FLAGS_Z al
OPCODE_EPILOG
; 4B
ALIGNC
EXPORT_C E0_PHK ; Push PB(K) onto stack
inc R_NativePC
mov al,B_PB
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHK
inc R_NativePC
mov al,B_PB
E1_PUSH_B
OPCODE_EPILOG
; 4C
ALIGNC
EXPORT_C ALL_JMP_a
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
ADDR_Absolute_JMP
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x4C
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 4D
EM_EOR a,Absolute
E0_EOR a,Absolute
; 4E
EM_LSR a,Absolute
E0_LSR a,Absolute
; 4F
EM_EOR al,Absolute_Long
E0_EOR al,Absolute_Long
; 50
BFC BVC,SNES_FLAG_V
; 51
EM_EOR OdO_y,Direct_Indirect_Indexed
E0_EOR OdO_y,Direct_Indirect_Indexed
; 52
EM_EOR OdO,Direct_Indirect
E0_EOR OdO,Direct_Indirect
; 53
EM_EOR Od_sO_y,Stack_Relative_Indirect_Indexed
E0_EOR Od_sO_y,Stack_Relative_Indirect_Indexed
; 54
ALIGNC
EXPORT_C E0_MVN
push ebx ; Cycles per instruction iteration
.again:
mov al,[1+R_NativePC] ; Dest bank
mov bl,[2+R_NativePC] ; Src bank
mov B_DB,al
mov ax,B_X ; Src address
shl ebx,16
add ebx,eax
inc eax
mov B_X,ax
GET_BYTE
mov ebx,B_DB_Shifted
mov bx,B_Y ; Dest address
SET_BYTE
mov eax,B_A
inc ebx
sub eax,byte 1
mov B_Y,bx
jc .done
test R_Cycles,R_Cycles
jge .event
mov B_A,ax
add R_Cycles,[esp]
xor eax,eax
xor ebx,ebx
jmp .again
ALIGNC
.done:
add R_NativePC,byte 3
.event:
mov B_A,ax
pop edi
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_MVN
push ebx ; Cycles per instruction iteration
.again:
mov al,[1+R_NativePC] ; Dest bank
mov bl,[2+R_NativePC] ; Src bank
mov B_DB,al
mov al,B_X ; Src address
shl ebx,16
add ebx,eax
inc eax
mov B_X,al
GET_BYTE
mov ebx,B_DB_Shifted
mov bl,B_Y ; Dest address
SET_BYTE
mov eax,B_A
inc ebx
sub eax,byte 1
mov B_Y,bl
jc .done
test R_Cycles,R_Cycles
jge .event
mov B_A,ax
add R_Cycles,[esp]
xor eax,eax
xor ebx,ebx
jmp short .again
ALIGNC
.done:
add R_NativePC,byte 3
.event:
mov B_A,ax
pop edi
OPCODE_EPILOG
; 55
EM_EOR d_x,Direct_Index_X
E0_EOR d_x,Direct_Index_X
; 56
EM_LSR d_x,Direct_Index_X
E0_LSR d_x,Direct_Index_X
; 57
EM_EOR IdI_y,Direct_Indirect_Indexed_Long
E0_EOR IdI_y,Direct_Indirect_Indexed_Long
; 58
ALIGNC
EXPORT_C E0_CLI
inc R_NativePC
STORE_FLAGS_I ah
mov al,[IRQ_pin]
test al,al
jz near CPU_RETURN
SAVE_PC ebx
add R_Cycles,byte 60 ; IRQ processing: 2 IO + 6 bank0
call E0_IRQ
LOAD_PC
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_CLI
inc R_NativePC
STORE_FLAGS_I ah
mov al,[IRQ_pin]
test al,al
jz near CPU_RETURN
SAVE_PC ebx
add R_Cycles,byte 52 ; IRQ processing: 2 IO + 5 bank0
call E1_IRQ
LOAD_PC
OPCODE_EPILOG
; 59
EM_EOR a_y,Absolute_Index_Y
E0_EOR a_y,Absolute_Index_Y
; 5A
ALIGNC
EXPORT_C E0_PHY
inc R_NativePC
mov eax,B_Y
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_PHY
inc R_NativePC
mov eax,B_Y
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHY
inc R_NativePC
mov eax,B_Y
E1_PUSH_B
OPCODE_EPILOG
; 5B
ALIGNC
EXPORT_C ALL_TCD
inc R_NativePC
mov eax,B_A
mov B_D,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 5C
ALIGNC
EXPORT_C ALL_JML_al
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
mov al,[1+R_NativePC]
xor ebx,ebx
mov ah,[2+R_NativePC]
mov bl,[3+R_NativePC]
mov B_PB,bl
mov R_NativePC,eax
test [MEMSEL],bl ; Check bus speed against PB
mov al,5
jnz .fastrom
mov al,4
.fastrom:
mov [CycleTable],al ; Update bus speed
mov edi,R_NativePC
shl ebx,16
or edi,ebx
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,ebx
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x5C
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 5D
EM_EOR a_x,Absolute_Index_X
E0_EOR a_x,Absolute_Index_X
; 5E
EM_LSR a_x,Absolute_Index_X
E0_LSR a_x,Absolute_Index_X
; 5F
EM_EOR al_x,Absolute_Long_Index_X
E0_EOR al_x,Absolute_Long_Index_X
; 60
ALIGNC
EXPORT_C E0_RTS
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E0_PULL_W
inc ax ; This is a MAD processor!
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x60
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
ALIGNC
EXPORT_C E1_RTS
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E1_PULL_W
inc ax ; This is a MAD processor!
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x60
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 61
EM_ADC Od_xO,Direct_Indexed_Indirect
E0_ADC Od_xO,Direct_Indexed_Indirect
; 62
ALIGNC
EXPORT_C E0_PER
mov al,[1+R_NativePC]
mov ah,[2+R_NativePC]
add R_NativePC,byte 3
GET_PC ebx
add eax,ebx
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PER
mov al,[1+R_NativePC]
mov ah,[2+R_NativePC]
add R_NativePC,byte 3
GET_PC ebx
add eax,ebx
E1_PUSH_W
OPCODE_EPILOG
; 63
EM_ADC d_s,Stack_Relative
E0_ADC d_s,Stack_Relative
; 64
;EM_STZ d,Direct
ALIGNC
EM_STZ d,Direct
E0_STZ d,Direct
; 65
EM_ADC d,Direct
E0_ADC d,Direct
; 66
EM_ROR d,Direct
E0_ROR d,Direct
; 67
EM_ADC IdI,Direct_Indirect_Long
E0_ADC IdI,Direct_Indirect_Long
; 68
ALIGNC
EXPORT_C E0_PLA
inc R_NativePC
E0_PULL_W
mov B_A,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
ALIGNC
EXPORT_C EM_PLA
inc R_NativePC
E0_PULL_B
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PLA
inc R_NativePC
E1_PULL_B
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
; 69
EM_ADC i,Immediate
E0_ADC i,Immediate
; 6A ; Fixed 0.25: RRA8 didn't set NZ flags correctly
ALIGNC
EXPORT_C EM_RRA
mov cl,B_C_flag
mov al,B_A
inc R_NativePC
add cl,255 ;MAKE_CARRY
rcr al,1
sbb cl,cl
mov B_A,al
STORE_FLAGS_NZC al,cl
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_RRA
mov cl,B_C_flag
mov eax,B_A
inc R_NativePC
add cl,255 ;MAKE_CARRY
rcr ax,1
sbb cl,cl
STORE_FLAGS_N ah
mov B_A,eax
or al,ah
STORE_FLAGS_C cl
STORE_FLAGS_Z al
OPCODE_EPILOG
; 6B
ALIGNC
EXPORT_C E0_RTL
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E0_PULL_W
inc ax ; This is a MAD processor!
mov R_NativePC,eax
E0_PULL_B
mov B_PB,al
test [MEMSEL],al ; Check bus speed against PB
mov bl,5
jnz .fastrom
mov bl,4
.fastrom:
mov ah,0
mov [CycleTable],bl ; Update bus speed
mov edi,R_NativePC
shl eax,16
or edi,eax
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,eax
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x6B
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
ALIGNC
EXPORT_C E1_RTL
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
E1_PULL_W
inc ax ; This is a MAD processor!
mov R_NativePC,eax
E1_PULL_B
mov B_PB,al
test [MEMSEL],al ; Check bus speed against PB
mov bl,5
jnz .fastrom
mov bl,4
.fastrom:
mov ah,0
mov [CycleTable],bl ; Update bus speed
mov edi,R_NativePC
shl eax,16
or edi,eax
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,eax
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x6B
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 6C
; JMP Absolute Indirect
; Returns PCH in %al
; PC = (a16)
;
ALIGNC
EXPORT_C ALL_JMP_OaO
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
mov bl,[1+R_NativePC]
mov bh,[2+R_NativePC]
GET_BYTE
inc ebx
mov ah,al
GET_BYTE
ror ax,8
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x6C
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 6D
EM_ADC a,Absolute
E0_ADC a,Absolute
; 6E
EM_ROR a,Absolute
E0_ROR a,Absolute
; 6F
EM_ADC al,Absolute_Long
E0_ADC al,Absolute_Long
; 70
BFS BVS,SNES_FLAG_V
; 71
EM_ADC OdO_y,Direct_Indirect_Indexed
E0_ADC OdO_y,Direct_Indirect_Indexed
; 72
EM_ADC OdO,Direct_Indirect
E0_ADC OdO,Direct_Indirect
; 73
EM_ADC Od_sO_y,Stack_Relative_Indirect_Indexed
E0_ADC Od_sO_y,Stack_Relative_Indirect_Indexed
; 74
EM_STZ d_x,Direct_Index_X
E0_STZ d_x,Direct_Index_X
; 75
EM_ADC d_x,Direct_Index_X
E0_ADC d_x,Direct_Index_X
; 76
EM_ROR d_x,Direct_Index_X
E0_ROR d_x,Direct_Index_X
; 77
EM_ADC IdI_y,Direct_Indirect_Indexed_Long
E0_ADC IdI_y,Direct_Indirect_Indexed_Long
; 78
ALIGNC
EXPORT_C ALL_SEI
mov al,1
inc R_NativePC
STORE_FLAGS_I al
OPCODE_EPILOG
; 79
EM_ADC a_y,Absolute_Index_Y
E0_ADC a_y,Absolute_Index_Y
; 7A
ALIGNC
EXPORT_C E0_PLY
inc R_NativePC
E0_PULL_W
mov B_Y,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_PLY
inc R_NativePC
E0_PULL_B
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PLY
inc R_NativePC
E1_PULL_B
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
; 7B
ALIGNC
EXPORT_C ALL_TDC
inc R_NativePC
mov eax,B_D
mov B_A,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 7C
ALIGNC
EXPORT_C ALL_JMP_Oa_xO
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
ADDR_Absolute_Indexed_Indirect
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x7C
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 7D
EM_ADC a_x,Absolute_Index_X
E0_ADC a_x,Absolute_Index_X
; 7E
EM_ROR a_x,Absolute_Index_X
E0_ROR a_x,Absolute_Index_X
; 7F
EM_ADC al_x,Absolute_Long_Index_X
E0_ADC al_x,Absolute_Long_Index_X
; 80
ALIGNC
EXPORT_C ALL_BRA
movsx eax,byte [1+R_NativePC]
add R_NativePC,byte 2
add R_NativePC,eax
OPCODE_EPILOG
; 81
EM_STA Od_xO,Direct_Indexed_Indirect
E0_STA Od_xO,Direct_Indexed_Indirect
; 82
ALIGNC
EXPORT_C ALL_BRL ; Branch always long (-32768 to 32767)
mov al,[1+R_NativePC]
GET_PC ebx
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],ebx
%endif
mov ah,[2+R_NativePC]
add ebx,byte 3
add eax,ebx
and eax,0xFFFF
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0x82
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; 83
EM_STA d_s,Stack_Relative
E0_STA d_s,Stack_Relative
; 84
EX_STY d,Direct
E0_STY d,Direct
; 85
EM_STA d,Direct
E0_STA d,Direct
; 86
EX_STX d,Direct
E0_STX d,Direct
; 87
EM_STA IdI,Direct_Indirect_Long
E0_STA IdI,Direct_Indirect_Long
; 88
ALIGNC
EXPORT_C EX_DEY
mov al,B_Y
inc R_NativePC
dec al
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_DEY
mov eax,B_Y
inc R_NativePC
dec eax
mov B_Y,ax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 89 ; Differs from norm, only sets Z flag
ALIGNC
EXPORT_C EM_BIT_i
mov al,[1+R_NativePC]
mov cl,B_A
add R_NativePC,byte 2
and al,cl
STORE_FLAGS_Z al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_BIT_i
mov al,[1+R_NativePC]
mov ecx,B_A
mov ah,[2+R_NativePC]
add R_NativePC,byte 3
and eax,ecx
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 8A
ALIGNC
EXPORT_C EM_TXA
inc R_NativePC
mov al,B_X
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TXA
inc R_NativePC
mov eax,B_X
mov B_A,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 8B
ALIGNC
EXPORT_C E0_PHB
inc R_NativePC
mov al,B_DB
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHB
inc R_NativePC
mov al,B_DB
E1_PUSH_B
OPCODE_EPILOG
; 8C
EX_STY a,Absolute
E0_STY a,Absolute
; 8D
EM_STA a,Absolute
E0_STA a,Absolute
; 8E
EX_STX a,Absolute
E0_STX a,Absolute
; 8F
EM_STA al,Absolute_Long
E0_STA al,Absolute_Long
; 90
BFC BCC,SNES_FLAG_C
; 91
EM_STA OdO_y,Direct_Indirect_Indexed
E0_STA OdO_y,Direct_Indirect_Indexed
; 92
EM_STA OdO,Direct_Indirect
E0_STA OdO,Direct_Indirect
; 93
EM_STA Od_sO_y,Stack_Relative_Indirect_Indexed
E0_STA Od_sO_y,Stack_Relative_Indirect_Indexed
; 94
EX_STY d_x,Direct_Index_X
E0_STY d_x,Direct_Index_X
; 95
EM_STA d_x,Direct_Index_X
E0_STA d_x,Direct_Index_X
; 96
EX_STX d_y,Direct_Index_Y
E0_STX d_y,Direct_Index_Y
; 97
EM_STA IdI_y,Direct_Indirect_Indexed_Long
E0_STA IdI_y,Direct_Indirect_Indexed_Long
; 98
ALIGNC
EXPORT_C EM_TYA
inc R_NativePC
mov al,B_Y
mov B_A,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TYA
inc R_NativePC
mov eax,B_Y
mov B_A,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 99
EM_STA a_y,Absolute_Index_Y
E0_STA a_y,Absolute_Index_Y
; 9A
ALIGNC
EXPORT_C E0_TXS
inc R_NativePC
mov eax,B_X
mov B_S,eax
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_TXS
inc R_NativePC
mov al,B_X
mov B_S,al
OPCODE_EPILOG
; 9B
ALIGNC
EXPORT_C EX_TXY
inc R_NativePC
mov al,B_X
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TXY
inc R_NativePC
mov eax,B_X
mov B_Y,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; 9C
EM_STZ a,Absolute
E0_STZ a,Absolute
; 9D
EM_STA a_x,Absolute_Index_X
E0_STA a_x,Absolute_Index_X
; 9E
EM_STZ a_x,Absolute_Index_X
E0_STZ a_x,Absolute_Index_X
; 9F
EM_STA al_x,Absolute_Long_Index_X
E0_STA al_x,Absolute_Long_Index_X
; A0
EX_LDY i,Immediate
E0_LDY i,Immediate
; A1
EM_LDA Od_xO,Direct_Indexed_Indirect
E0_LDA Od_xO,Direct_Indexed_Indirect
; A2
EX_LDX i,Immediate
E0_LDX i,Immediate
; A3
EM_LDA d_s,Stack_Relative
E0_LDA d_s,Stack_Relative
; A4
EX_LDY d,Direct
E0_LDY d,Direct
; A5
EM_LDA d,Direct
E0_LDA d,Direct
; A6
EX_LDX d,Direct
E0_LDX d,Direct
; A7
EM_LDA IdI,Direct_Indirect_Long
E0_LDA IdI,Direct_Indirect_Long
; A8
ALIGNC
EXPORT_C EX_TAY
inc R_NativePC
mov al,B_A
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TAY
inc R_NativePC
mov eax,B_A
mov B_Y,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; A9
EM_LDA i,Immediate
E0_LDA i,Immediate
; AA
ALIGNC
EXPORT_C EX_TAX
inc R_NativePC
mov al,B_A
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TAX
inc R_NativePC
mov eax,B_A
mov B_X,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; AB
ALIGNC
EXPORT_C E0_PLB
inc R_NativePC
E0_PULL_B
mov B_DB,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PLB
inc R_NativePC
E1_PULL_B
mov B_DB,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
; AC
EX_LDY a,Absolute
E0_LDY a,Absolute
; AD
EM_LDA a,Absolute
E0_LDA a,Absolute
; AE
EX_LDX a,Absolute
E0_LDX a,Absolute
; AF
EM_LDA al,Absolute_Long
E0_LDA al,Absolute_Long
; B0
BFS BCS,SNES_FLAG_C
; B1
EM_LDA OdO_y,Direct_Indirect_Indexed
E0_LDA OdO_y,Direct_Indirect_Indexed
; B2
EM_LDA OdO,Direct_Indirect
E0_LDA OdO,Direct_Indirect
; B3
EM_LDA Od_sO_y,Stack_Relative_Indirect_Indexed
E0_LDA Od_sO_y,Stack_Relative_Indirect_Indexed
; B4
EX_LDY d_x,Direct_Index_X
E0_LDY d_x,Direct_Index_X
; B5
EM_LDA d_x,Direct_Index_X
E0_LDA d_x,Direct_Index_X
; B6
EX_LDX d_y,Direct_Index_Y
E0_LDX d_y,Direct_Index_Y
; B7
EM_LDA IdI_y,Direct_Indirect_Indexed_Long
E0_LDA IdI_y,Direct_Indirect_Indexed_Long
; B8
ALIGNC
EXPORT_C ALL_CLV
inc R_NativePC
STORE_FLAGS_V ah
OPCODE_EPILOG
; B9
EM_LDA a_y,Absolute_Index_Y
E0_LDA a_y,Absolute_Index_Y
; BA
ALIGNC
EXPORT_C EX_TSX
inc R_NativePC
mov al,B_S
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TSX
inc R_NativePC
mov eax,B_S
mov B_X,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; BB
ALIGNC
EXPORT_C EX_TYX
inc R_NativePC
mov al,B_Y
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_TYX
inc R_NativePC
mov eax,B_Y
mov B_X,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; BC
EX_LDY a_x,Absolute_Index_X
E0_LDY a_x,Absolute_Index_X
; BD
EM_LDA a_x,Absolute_Index_X
E0_LDA a_x,Absolute_Index_X
; BE
EX_LDX a_y,Absolute_Index_Y
E0_LDX a_y,Absolute_Index_Y
; BF
EM_LDA al_x,Absolute_Long_Index_X
E0_LDA al_x,Absolute_Long_Index_X
; C0
EX_CPY i,Immediate
E0_CPY i,Immediate
; C1
EM_CMP Od_xO,Direct_Indexed_Indirect
E0_CMP Od_xO,Direct_Indexed_Indirect
; C2
ALIGNC
EXPORT_C E0_REP
mov al,[1+R_NativePC]
test al,REAL_SNES_FLAG_C
jz .no_change_carry
STORE_FLAGS_C ah
.no_change_carry:
test al,REAL_SNES_FLAG_Z
jz .no_change_zero
STORE_FLAGS_Z al
.no_change_zero:
test al,REAL_SNES_FLAG_I
jz .no_change_interrupt_disable
STORE_FLAGS_I ah
.no_change_interrupt_disable:
test al,REAL_SNES_FLAG_D
jz .no_change_decimal_mode
STORE_FLAGS_D ah
.no_change_decimal_mode:
test al,REAL_SNES_FLAG_X
jz .no_change_index_size
STORE_FLAGS_X ah
.no_change_index_size:
test al,REAL_SNES_FLAG_M
jz .no_change_memory_size
STORE_FLAGS_M ah
.no_change_memory_size:
test al,REAL_SNES_FLAG_V
jz .no_change_overflow
STORE_FLAGS_V ah
.no_change_overflow:
test al,REAL_SNES_FLAG_N
jz .no_change_negative
STORE_FLAGS_N ah
.no_change_negative:
add R_NativePC,byte 2
JUMP_FLAG SNES_FLAG_I,.no_irq
mov al,[IRQ_pin]
test al,al
jz .no_irq
SAVE_PC ebx
add R_Cycles,byte 60 ; IRQ processing: 2 IO + 6 bank0
call E0_IRQ
LOAD_PC
.no_irq:
SET_TABLE_MX
ALIGNC
EXPORT_C E1_REP
mov al,[1+R_NativePC]
test al,REAL_SNES_FLAG_C
jz .no_change_carry
STORE_FLAGS_C ah
.no_change_carry:
test al,REAL_SNES_FLAG_Z
jz .no_change_zero
STORE_FLAGS_Z al
.no_change_zero:
test al,REAL_SNES_FLAG_I
jz .no_change_interrupt_disable
STORE_FLAGS_I ah
.no_change_interrupt_disable:
test al,REAL_SNES_FLAG_D
jz .no_change_decimal_mode
STORE_FLAGS_D ah
.no_change_decimal_mode:
test al,REAL_SNES_FLAG_V
jz .no_change_overflow
STORE_FLAGS_V ah
.no_change_overflow:
test al,REAL_SNES_FLAG_N
jz .no_change_negative
STORE_FLAGS_N ah
.no_change_negative:
add R_NativePC,byte 2
JUMP_FLAG SNES_FLAG_I,CPU_RETURN,near
mov al,[IRQ_pin]
test al,al
jz near CPU_RETURN
SAVE_PC ebx
add R_Cycles,byte 52 ; IRQ processing: 2 IO + 5 bank0
call E1_IRQ
LOAD_PC
OPCODE_EPILOG
; C3
EM_CMP d_s,Stack_Relative
E0_CMP d_s,Stack_Relative
; C4
EX_CPY d,Direct
E0_CPY d,Direct
; C5
EM_CMP d,Direct
E0_CMP d,Direct
; C6
EM_DEC d,Direct
E0_DEC d,Direct
; C7
EM_CMP IdI,Direct_Indirect_Long
E0_CMP IdI,Direct_Indirect_Long
; C8
ALIGNC
EXPORT_C EX_INY
mov al,B_Y
inc R_NativePC
inc al
mov B_Y,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_INY
mov eax,B_Y
inc R_NativePC
inc eax
mov B_Y,ax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; C9
EM_CMP i,Immediate
E0_CMP i,Immediate
; CA
ALIGNC
EXPORT_C EX_DEX
mov al,B_X
inc R_NativePC
dec al
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_DEX
mov eax,B_X
inc R_NativePC
dec eax
mov B_X,ax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; CB
ALIGNC
EXPORT_C ALL_WAI ; Wait for interrupt
mov al,[IRQ_pin]
test al,al
jnz .irq_active
%ifndef ADD_CYCLES_FIRST
pop ebx
add R_Cycles,ebx
%endif
; Put CPU in WAI mode
mov byte [CPU_Execution_Mode],CEM_Waiting_For_Interrupt
; Trigger next event
test R_Cycles,R_Cycles
jge near HANDLE_EVENT
xor R_Cycles,R_Cycles
jmp HANDLE_EVENT
ALIGNC
.irq_active:
inc R_NativePC
; WAI delay after interrupt signal: 2 IO
;add R_Cycles,byte 12 ;*
OPCODE_EPILOG
; CC
EX_CPY a,Absolute
E0_CPY a,Absolute
; CD
EM_CMP a,Absolute
E0_CMP a,Absolute
; CE
EM_DEC a,Absolute
E0_DEC a,Absolute
; CF
EM_CMP al,Absolute_Long
E0_CMP al,Absolute_Long
; D0
BFC BNE,SNES_FLAG_Z
; D1
EM_CMP OdO_y,Direct_Indirect_Indexed
E0_CMP OdO_y,Direct_Indirect_Indexed
; D2
EM_CMP OdO,Direct_Indirect
E0_CMP OdO,Direct_Indirect
; D3
EM_CMP Od_sO_y,Stack_Relative_Indirect_Indexed
E0_CMP Od_sO_y,Stack_Relative_Indirect_Indexed
; D4
ALIGNC
EXPORT_C E0_PEI
READ16_Direct
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PEI
READ16_Direct
E1_PUSH_W
OPCODE_EPILOG
; D5
EM_CMP d_x,Direct_Index_X
E0_CMP d_x,Direct_Index_X
; D6
EM_DEC d_x,Direct_Index_X
E0_DEC d_x,Direct_Index_X
; D7
EM_CMP IdI_y,Direct_Indirect_Indexed_Long
E0_CMP IdI_y,Direct_Indirect_Indexed_Long
; D8
ALIGNC
EXPORT_C ALL_CLD
inc R_NativePC
STORE_FLAGS_D ah
OPCODE_EPILOG
; D9
EM_CMP a_y,Absolute_Index_Y
E0_CMP a_y,Absolute_Index_Y
; DA
ALIGNC
EXPORT_C E0_PHX
inc R_NativePC
mov eax,B_X
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_PHX
inc R_NativePC
mov eax,B_X
E0_PUSH_B
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PHX
inc R_NativePC
mov eax,B_X
E1_PUSH_B
OPCODE_EPILOG
; DB
ALIGNC
EXPORT_C ALL_STP
%ifndef ADD_CYCLES_FIRST
pop ebx
add R_Cycles,ebx
%endif
; Put CPU in STP mode
mov byte [CPU_Execution_Mode],CEM_Clock_Stopped
; Trigger next event
test R_Cycles,R_Cycles
jge near HANDLE_EVENT
xor R_Cycles,R_Cycles
jmp HANDLE_EVENT
; DC
; JML Absolute Indirect Long
; PB:PC = [a16]
;
ALIGNC
EXPORT_C ALL_JML_OaO
%ifdef TRAP_INVALID_JUMP
GET_PC eax
mov [_Map_Byte],eax
%endif
mov bl,[1+R_NativePC]
mov bh,[2+R_NativePC]
GET_BYTE
inc ebx
mov ah,al
GET_BYTE
ror ax,8
inc ebx
mov R_NativePC,eax
GET_BYTE
mov B_PB,al
test [MEMSEL],al ; Check bus speed against PB
mov bl,5
jnz .fastrom
mov bl,4
.fastrom:
mov ah,0
mov [CycleTable],bl ; Update bus speed
mov edi,R_NativePC
shl eax,16
or edi,eax
shr edi,13
mov edi,[_Read_Bank8Offset+edi*4]
test edi,edi
jz .read_non_linear
add edi,eax
.read_direct:
add R_NativePC,edi
mov B_PBOffset,edi
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0xDC
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov edi,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; DD
EM_CMP a_x,Absolute_Index_X
E0_CMP a_x,Absolute_Index_X
; DE
EM_DEC a_x,Absolute_Index_X
E0_DEC a_x,Absolute_Index_X
; DF
EM_CMP al_x,Absolute_Long_Index_X
E0_CMP al_x,Absolute_Long_Index_X
; E0
EX_CPX i,Immediate
E0_CPX i,Immediate
; E1
EM_SBC Od_xO,Direct_Indexed_Indirect
E0_SBC Od_xO,Direct_Indexed_Indirect
; E2
ALIGNC
EXPORT_C E0_SEP
mov al,[1+R_NativePC]
test al,REAL_SNES_FLAG_C
jz .no_change_carry
STORE_FLAGS_C al
.no_change_carry:
test al,REAL_SNES_FLAG_Z
jz .no_change_zero
STORE_FLAGS_Z ah
.no_change_zero:
test al,REAL_SNES_FLAG_I
jz .no_change_interrupt_disable
STORE_FLAGS_I al
.no_change_interrupt_disable:
test al,REAL_SNES_FLAG_D
jz .no_change_decimal_mode
STORE_FLAGS_D al
.no_change_decimal_mode:
test al,REAL_SNES_FLAG_X
jz .no_change_index_size
STORE_FLAGS_X al
.no_change_index_size:
test al,REAL_SNES_FLAG_M
jz .no_change_memory_size
STORE_FLAGS_M al
.no_change_memory_size:
test al,REAL_SNES_FLAG_V
jz .no_change_overflow
STORE_FLAGS_V al
.no_change_overflow:
test al,REAL_SNES_FLAG_N
jz .no_change_negative
STORE_FLAGS_N al
.no_change_negative:
add R_NativePC,byte 2
SET_TABLE_MX
ALIGNC
EXPORT_C E1_SEP
mov al,[1+R_NativePC]
test al,REAL_SNES_FLAG_C
jz .no_change_carry
STORE_FLAGS_C al
.no_change_carry:
test al,REAL_SNES_FLAG_Z
jz .no_change_zero
STORE_FLAGS_Z ah
.no_change_zero:
test al,REAL_SNES_FLAG_I
jz .no_change_interrupt_disable
STORE_FLAGS_I al
.no_change_interrupt_disable:
test al,REAL_SNES_FLAG_D
jz .no_change_decimal_mode
STORE_FLAGS_D al
.no_change_decimal_mode:
test al,REAL_SNES_FLAG_V
jz .no_change_overflow
STORE_FLAGS_V al
.no_change_overflow:
test al,REAL_SNES_FLAG_N
jz .no_change_negative
STORE_FLAGS_N al
.no_change_negative:
add R_NativePC,byte 2
OPCODE_EPILOG
; E3
EM_SBC d_s,Stack_Relative
E0_SBC d_s,Stack_Relative
; E4
EX_CPX d,Direct
E0_CPX d,Direct
; E5
EM_SBC d,Direct
E0_SBC d,Direct
; E6
EM_INC d,Direct
E0_INC d,Direct
; E7
EM_SBC IdI,Direct_Indirect_Long
E0_SBC IdI,Direct_Indirect_Long
; E8
ALIGNC
EXPORT_C EX_INX
mov al,B_X
inc R_NativePC
inc al
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E0_INX
mov eax,B_X
inc R_NativePC
inc eax
mov B_X,ax
or al,ah
STORE_FLAGS_N ah
STORE_FLAGS_Z al
OPCODE_EPILOG
; E9
EM_SBC i,Immediate
E0_SBC i,Immediate
; EA
ALIGNC
EXPORT_C ALL_NOP
inc R_NativePC
OPCODE_EPILOG
; EB
ALIGNC
EXPORT_C ALL_XBA
mov ah,B_A
inc R_NativePC
mov al,B_B
STORE_FLAGS_NZ al
mov B_A,eax
OPCODE_EPILOG
; EC
EX_CPX a,Absolute
E0_CPX a,Absolute
; ED
EM_SBC a,Absolute
E0_SBC a,Absolute
; EE
EM_INC a,Absolute
E0_INC a,Absolute
; EF
EM_SBC al,Absolute_Long
E0_SBC al,Absolute_Long
; F0
BFS BEQ,SNES_FLAG_Z
; F1
EM_SBC OdO_y,Direct_Indirect_Indexed
E0_SBC OdO_y,Direct_Indirect_Indexed
; F2
EM_SBC OdO,Direct_Indirect
E0_SBC OdO,Direct_Indirect
; F3
EM_SBC Od_sO_y,Stack_Relative_Indirect_Indexed
E0_SBC Od_sO_y,Stack_Relative_Indirect_Indexed
; F4
ALIGNC
EXPORT_C E0_PEA
mov al,[1+R_NativePC]
mov ah,[2+R_NativePC]
add R_NativePC,byte 3
E0_PUSH_W
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PEA
mov al,[1+R_NativePC]
mov ah,[2+R_NativePC]
add R_NativePC,byte 3
E1_PUSH_W
OPCODE_EPILOG
; F5
EM_SBC d_x,Direct_Index_X
E0_SBC d_x,Direct_Index_X
; F6
EM_INC d_x,Direct_Index_X
E0_INC d_x,Direct_Index_X
; F7
EM_SBC IdI_y,Direct_Indirect_Indexed_Long
E0_SBC IdI_y,Direct_Indirect_Indexed_Long
; F8
ALIGNC
EXPORT_C ALL_SED
mov al,1
inc R_NativePC
STORE_FLAGS_D al
OPCODE_EPILOG
; F9
EM_SBC a_y,Absolute_Index_Y
E0_SBC a_y,Absolute_Index_Y
; FA
ALIGNC
EXPORT_C E0_PLX
inc R_NativePC
E0_PULL_W
mov B_X,eax
STORE_FLAGS_N ah
or al,ah
STORE_FLAGS_Z al
OPCODE_EPILOG
ALIGNC
EXPORT_C EX_PLX
inc R_NativePC
E0_PULL_B
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_PLX
inc R_NativePC
E1_PULL_B
mov B_X,al
STORE_FLAGS_NZ al
OPCODE_EPILOG
; FB
ALIGNC
EXPORT_C E0_XCE
inc R_NativePC
JUMP_NOT_FLAG SNES_FLAG_C,CPU_RETURN,near
mov B_XH,ah
mov B_YH,ah
STORE_FLAGS_C ah
mov al,1
STORE_FLAGS_E al
STORE_FLAGS_B al
STORE_FLAGS_1 al
mov B_SH,al
mov dword [OpTable],OpTableE1 ; Set current opcode emulation table
OPCODE_EPILOG
ALIGNC
EXPORT_C E1_XCE
inc R_NativePC
JUMP_FLAG SNES_FLAG_C,CPU_RETURN,near
STORE_FLAGS_E ah
mov al,1
STORE_FLAGS_C al
STORE_FLAGS_M al
STORE_FLAGS_X al
mov dword [OpTable],OpTableMX ; Set current opcode emulation table
OPCODE_EPILOG
; FC
ALIGNC
EXPORT_C E0_JSR_Oa_xO
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 2 ; last instruction byte PC in ax
E0_PUSH_W ; Address of last byte not next instruction (huh!)
ADDR_Absolute_Indexed_Indirect
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0xFC
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
ALIGNC
EXPORT_C E1_JSR_Oa_xO
GET_PC eax
%ifdef TRAP_INVALID_JUMP
mov [_Map_Byte],eax
%endif
add eax,byte 2 ; last instruction byte PC in ax
E1_PUSH_W ; Address of last byte not next instruction (huh!)
ADDR_Absolute_Indexed_Indirect
mov ebx,B_PB_Shifted
mov R_NativePC,eax
or eax,ebx
shr eax,13
mov eax,[_Read_Bank8Offset+eax*4]
test eax,eax
jz .read_non_linear
add eax,ebx
.read_direct:
add R_NativePC,eax
mov B_PBOffset,eax
OPCODE_EPILOG
.read_non_linear:
%ifdef TRAP_INVALID_JUMP
mov byte [_Map_Byte+3],0xFC
mov [_Map_Address],ebx
jmp _InvalidJump
%else
mov eax,_Blank ;we should really trap this...
jmp short .read_direct
%endif
; FD
EM_SBC a_x,Absolute_Index_X
E0_SBC a_x,Absolute_Index_X
; FE
EM_INC a_x,Absolute_Index_X
E0_INC a_x,Absolute_Index_X
; FF
EM_SBC al_x,Absolute_Long_Index_X
E0_SBC al_x,Absolute_Long_Index_X