www.pudn.com > Adnence_add8.rar > adder8bit.vhd, change:2002-06-18,size:1211b


LIBRARY IEEE; 
USE IEEE.std_logic_1164.ALL; 
USE IEEE.std_logic_ARITH.ALL; 
USE IEEE.std_logic_UNSIGNED.ALL; 
 
ENTITY ADDER8BIT IS 
	--*********************************************** 
	--*		A, B:加数,被加数      CI:进位输入		* 
	--*		Y_OUT:和输出          CO_OUT:进位输出	* 
	--*********************************************** 
	PORT(A, B: IN UNSIGNED(7 downto 0); 
		CI,clk: IN STD_LOGIC; 
		Y_OUT: OUT STD_LOGIC_VECTOR(7 downto 0); 
		CO_OUT: OUT	STD_LOGIC); 
END ADDER8BIT; 
 
ARCHITECTURE doing OF ADDER8BIT IS 
	--*********************************************** 
	--*		Y:和          CO:进位					* 
	--*********************************************** 
	SIGNAL CO,Y: STD_LOGIC_VECTOR(7 downto 0); 
BEGIN 
	Y(0)<=A(0) xor B(0) xor CI; 
	CO(0)<=(A(0) and B(0)) or (B(0) and CI) or (A(0) and CI); 
	GEN: 
		for i in 1 to 7 GENERATE 
			--********求Y(i)和Co(i)******** 
			Y(i)<=A(i) xor B(i) xor CO(i-1); 
			CO(i)<=(CO(i-1) and A(i)) or (CO(i-1) and B(i)) or (A(i) and B(i)); 
		end GENERATE; 
	process(clk) 
	begin		 
		if clk'event and clk='1' then 
			--********输出********* 
			Y_OUT<=Y(7) & Y(6) & Y(5) & Y(4) & Y(3) & Y(2) & Y(1) & Y(0); 
			CO_OUT<=CO(7); 
		end if; 
	end process; 
END doing;