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; *******************************************************
; * NAME : INIT.S *
; * Version : 28.May.2003 *
; * Description: *
; * C start up codes *
; * Configure memory, Initialize ISR ,stacks *
; * Initialize C-variables *
; * Fill zeros into zero-initialized C-variables *
; *******************************************************
GET ..\inc\memcfg.inc
GET ..\inc\miscel.inc
;Memory Area
;GCS6 64M 16bit(8MB) SDRAM(0xc000000-0xc7fffff)
;APP RAM=0xc000000~0xc7effff
;44BMON RAM=0xc7f0000-0xc7fffff
;STACK =0xc7ffa00
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT bios_main
CODE32 ;for start-up code for Thumb mode
AREA Init,CODE,READONLY
ENTRY
b ResetHandler ;for debug
b HandlerUndef ;handlerUndef
b HandlerSWI ;SWI interrupt handler
b HandlerPabort ;handlerPAbort
b HandlerDabort ;handlerDAbort
b . ;handlerReserved
b HandlerIRQ ;handlerIRQ
b HandlerFIQ ;handlerFIQ
b HandlerEINT0
b HandlerEINT1
b HandlerEINT2
b HandlerEINT3
b HandlerEINT4567
b .
b .
b HandlerTICK
b HandlerZDMA0
b HandlerZDMA1
b HandlerBDMA0
b HandlerBDMA1
b HandlerWDT
b HandlerUERR01
b .
b .
b HandlerTIMER0
b HandlerTIMER1
b HandlerTIMER2
b HandlerTIMER3
b HandlerTIMER4
b HandlerTIMER5
b .
b .
b HandlerURXD0
b HandlerURXD1
b HandlerIIC
b HandlerSIO
b HandlerUTXD0
b HandlerUTXD1
b .
b .
b HandlerRTC
b .
b .
b .
b .
b .
b .
b HandlerADC
;****************************************************
;* START *
;****************************************************
ResetHandler
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0x07ffffff ;all interrupt disable
str r1,[r0]
;****************************************************
;* Set clock control registers *
;****************************************************
ldr r0,=LOCKTIME
ldr r1,=0xfff
str r1,[r0]
ldr r0,=PLLCON ;temporary setting of PLL
ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) ;Fin=8MHz,Fout=64MHz
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7ff8 ;All unit block CLK enable
str r1,[r0]
;****************************************
;* change BDMACON reset value for BDMA *
;****************************************
ldr r0,=BDIDES0
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0]
ldr r0,=BDIDES1
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0] ;DMA FOR IDE
;****************************************************
;* Set memory control registers *
;****************************************************
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=0x01c80000 ;BWSCON Address
stmia r0,{r1-r13}
;****************************************************
;* Initialize stacks *
;****************************************************
ldr sp, =SVCStack
bl InitStacks
;********************************************************
;* Copy and paste RW data/zero initialized data *
;********************************************************
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ;Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq %F1
0
cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
bcc %B0
1
ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
2
cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %B2
ldr r0,=0x1e00024
ldr r1,=0xffffffff
str r1,[r0] ;DMA FOR IDE
mrs r0,cpsr
bic r0,r0,#0x80
msr cpsr_cxsf,r0 ;UndefMode
b bios_main
;****************************************************
;* The function for initializing stack *
;****************************************************
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK
orr r1,r0,#SVCMODE|NOINT
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;USER mode is not initialized.
mov pc,lr ;The LR register may be not valid for the mode changes.
;****************************************************
;* The function for entering power down mode *
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;self-refresh enable
str r1, [r0]
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop ;mov r0, r0
nop
nop
nop
nop
;enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;wait until enter SL_IDLE,STOP mode and until wake-up
ldr r0,=0x10
0 subs r0,r0,#1
bne %B0
;exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
LTORG
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
HandlerADC HANDLER HandleADC
HandlerRTC HANDLER HandleRTC
HandlerUTXD1 HANDLER HandleUTXD1
HandlerUTXD0 HANDLER HandleUTXD0
HandlerSIO HANDLER HandleSIO
HandlerIIC HANDLER HandleIIC
HandlerURXD1 HANDLER HandleURXD1
HandlerURXD0 HANDLER HandleURXD0
HandlerTIMER5 HANDLER HandleTIMER5
HandlerTIMER4 HANDLER HandleTIMER4
HandlerTIMER3 HANDLER HandleTIMER3
HandlerTIMER2 HANDLER HandleTIMER2
HandlerTIMER1 HANDLER HandleTIMER1
HandlerTIMER0 HANDLER HandleTIMER0
HandlerUERR01 HANDLER HandleUERR01
HandlerWDT HANDLER HandleWDT
HandlerBDMA1 HANDLER HandleBDMA1
HandlerBDMA0 HANDLER HandleBDMA0
HandlerZDMA1 HANDLER HandleZDMA1
HandlerZDMA0 HANDLER HandleZDMA0
HandlerTICK HANDLER HandleTICK
HandlerEINT4567 HANDLER HandleEINT4567
HandlerEINT3 HANDLER HandleEINT3
HandlerEINT2 HANDLER HandleEINT2
HandlerEINT1 HANDLER HandleEINT1
HandlerEINT0 HANDLER HandleEINT0
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
;bank0 16bit BOOT ROM
;bank1 8bit NandFlash
;bank2 16bit IDE
;bank3 8bit UDB
;bank4 rtl8019
;bank5 ext
;bank6 16bit SDRAM
;bank7 16bit SDRAM
LTORG
SMRDATA DATA
DCD 0x11110101 ;Bank0=16bit BootRom(AT29C010A*2) :0x0
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x10 ;SCLK power down mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
AREA RamData, DATA, READWRITE
MAP (_VIDEO_ADDRESS)
Videodata FIELD 256*512
MAP (_ISR_STARTADDRESS-0x600)
UserStack FIELD 256 ;c7ffa00
SVCStack FIELD 256 ;c7ffb00
UndefStack FIELD 256 ;c7ffc00
AbortStack FIELD 256 ;c7ffd00
IRQStack FIELD 256 ;c7ffe00
FIQStack FIELD 0 ;c7fff00
MAP _ISR_STARTADDRESS
HandleReset FIELD 4
HandleUndef FIELD 4
HandleSWI FIELD 4
HandlePabort FIELD 4
HandleDabort FIELD 4
HandleReserved FIELD 4
HandleIRQ FIELD 4
HandleFIQ FIELD 4
HandleADC FIELD 4
HandleRTC FIELD 4
HandleUTXD1 FIELD 4
HandleUTXD0 FIELD 4
HandleSIO FIELD 4
HandleIIC FIELD 4
HandleURXD1 FIELD 4
HandleURXD0 FIELD 4
HandleTIMER5 FIELD 4
HandleTIMER4 FIELD 4
HandleTIMER3 FIELD 4
HandleTIMER2 FIELD 4
HandleTIMER1 FIELD 4
HandleTIMER0 FIELD 4
HandleUERR01 FIELD 4
HandleWDT FIELD 4
HandleBDMA1 FIELD 4
HandleBDMA0 FIELD 4
HandleZDMA1 FIELD 4
HandleZDMA0 FIELD 4
HandleTICK FIELD 4
HandleEINT4567 FIELD 4
HandleEINT3 FIELD 4
HandleEINT2 FIELD 4
HandleEINT1 FIELD 4
HandleEINT0 FIELD 4 ;0xc7fff84
END