www.pudn.com > 常用库元件.rar > Documents.LIBPKG


[Design] 
Version=1.0 
HierarchyMode=0 
ChannelRoomNamingStyle=0 
OutputPath= 
ChannelDesignatorFormatString=$Component_$RoomName 
ChannelRoomLevelSeperator=_ 
OpenOutputs=1 
ArchiveProject=0 
TimestampOutput=0 
SeparateFolders=0 
AllowPortNetNames=0 
AllowSheetEntryNetNames=1 
AppendSheetNumberToLocalNets=0 
DefaultConfiguration= 
UserID=0xFFFFFFFF 
 
[Document1] 
DocumentPath=555定时.LIB 
AnnotationEnabled=1 
AnnotateStartValue=1 
AnnotateSuffix= 
AnnotationIgnoreSelected=0 
AnnotateOrder=-1 
DoLibraryUpdate=1 
DoDatabaseUpdate=1 
 
[Document2] 
DocumentPath=8字数码管.Lib 
AnnotationEnabled=1 
AnnotateStartValue=1 
AnnotateSuffix= 
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DoLibraryUpdate=1 
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[Document3] 
DocumentPath=CMOS系列.Lib 
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[Document4] 
DocumentPath=TTL74系列.Lib 
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[Document5] 
DocumentPath=可控硅.Lib 
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[Document6] 
DocumentPath=场效应管.LIB 
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[Document7] 
DocumentPath=杂元件库.lib 
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[Document8] 
DocumentPath=电子管.LIB 
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[Document9] 
DocumentPath=电控开关.Lib 
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[OutputGroup1] 
Name=Netlist Outputs 
Description= 
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 
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OutputName1=EDIF for PCB 
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[OutputGroup2] 
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[OutputGroup3] 
Name=Documentation Outputs 
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[OutputGroup4] 
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OutputType2=Pick Place 
OutputName2=Generates pick and place files 
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[OutputGroup5] 
Name=Fabrication Outputs 
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OutputName6=NC Drill Files 
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OutputType9=Test Points 
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[OutputGroup6] 
Name=Report Outputs 
Description= 
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OutputName1=Bill of Materials 
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OutputType2=ComponentCrossReference 
OutputName2=Component Cross Reference Report 
OutputDocumentPath2= 
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OutputType3=ReportHierarchy 
OutputName3=Report Project Hierarchy 
OutputDocumentPath3= 
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OutputName4=Simple BOM 
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[OutputGroup7] 
Name=Other Outputs 
Description= 
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[Modification Levels] 
Type1=1 
Type2=1 
Type3=1 
Type4=1 
Type5=1 
Type6=1 
Type7=1 
Type8=1 
Type9=1 
Type10=1 
Type11=1 
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[Difference Levels] 
Type1=1 
Type2=1 
Type3=1 
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[Electrical Rules Check] 
Type1=1 
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[ERC Connection Matrix] 
L1=NNNNNNNNNNNWNNNWW 
L2=NNWNNNNWWWNWNWNWN 
L3=NWEENEEEENEWNEEWN 
L4=NNENNNWEENNWNENWN 
L5=NNNNNNNNNNNNNNNNN 
L6=NNENNNNEENNWNENWN 
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L8=NWEENEENEEENNEENN 
L9=NWEENEEEENEWNEEWW 
L10=NWNNNNNENNEWNNEWN 
L11=NNENNNNEEENWNENWN 
L12=WWWWNWWNWWWNWWWNN 
L13=NNNNNNNNNNNWNNNWW 
L14=NWEENEEEENEWNEEWW 
L15=NNENNNNEEENWNENWW 
L16=WWWWNWWNWWWNWWWNW 
L17=WNNNNNNNWNNNWWWWN 
 
[Annotate] 
SortOrder=3 
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[HighlightMethod] 
Zoom=1 
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Filter=1 
Graph=0 
IncludePower=0 
ZoomPrecision=100 
 
[DisplayedObject] 
Pin=1 
NetLabel=1 
Port=1 
CrossSheet=1 
SheetEntry=1 
SheetSymbol=1 
Part=0 
Component=0 
Net=0 
Bus=0 
Line=0 
 
[LibraryUpdateOptions] 
SelectedOnly=0 
FullReplace=1 
DoGraphics=1 
DoParameters=1 
DoModels=1 
AddParameters=0 
RemoveParameters=0 
AddModels=1 
RemoveModels=1 
UpdateCurrentModels=1 
 
[DatabaseUpdateOptions] 
SelectedOnly=0 
 
[Comparison Options] 
ComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 
ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 
ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 
ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0