www.pudn.com > 4510b_dma.rar > dma.h

/********************************************************************/ 
/*                                                                  */ 
/*       GDMA Header for KS32C50100                                 */ 
/*------------------------------------------------------------------*/ 
/*      Copyright (C) 1997 Samsung Electronics.                     */ 
/*------------------------------------------------------------------*/ 
/*                                                                  */ 
/*      Description : 1997-12-26 first edited                       */  
/********************************************************************/ 
 
#ifndef _GDMA_H_ 
#define _GDMA_H_ 
 
 
/* GDMA Control Register */ 
#define GDMA_RUN           0x0001 
#define GDMA_BUSY          0x0002 
 
#define GDMA_MODE          0x000C 
#define GDMA_MEM2MEM       0x0000 
#define GDMA_EXTDREQ       0x0004 
#define GDMA_U0MODE        0x0008 
#define GDMA_U1MODE        0x000C 
 
#define GDMA_DST_DEC       0x0010       
#define GDMA_SRC_DEC       0x0020       
#define GDMA_DST_FIX       0x0040       
#define GDMA_SRC_FIX       0x0080       
#define GDMA_INT_ENABLE    0x0100       
#define GDMA_RESET         0x0200   //Changed to Four-data burst enable bit   
#define GDMA_MEM2UART      0x0400   //Other case UART to MEM     
#define GDMA_BLOCK         0x0800   //Other case Single mode      
#define GDMA_TX_WIDTH      0x3000 
#define GDMA_TX_BYTE       0x0000    
#define GDMA_TX_HALFWORD   0x1000   
#define GDMA_TX_WORD       0x2000  
#define GDMA_NO_USE        0x3000  
#define GDMA_CONTINUOUS    0x4000  
#define GDMA_DEMAND        0x8000  
#define GDMA_WIDTH_BTYE		0 
#define GDMA_WIDTH_HWORD   (1<<12) 
#define GDMA_WIDTH_WORD	   (2<<12) 
 
#define GDMA1       '1' 
#define GDMA0       '0' 
 
/* Transfer Width */ 
#define TxBYTE   0 
#define TxHWORD  1 
#define TxWORD   2 
 
/* GDMA Registers */ 
typedef struct { 
        U32 CON;   //control register 
        U32 SRC;   //source address register 
        U32 DST;   //destination address register 
        U32 CNT;   //counter register 
        int DIALOG; //flag to control dialog or direct function test 
} GDMA_REG; 
 
 
extern void GdmaStartUserPgm(void); 
 
extern void GdmaTest(void); 
/* 
 * GDMA0/GDMA1 Test Top Module 
 */ 
 
extern void GDMAStartUpDialog(void); 
/* 
 * GDMA Register setup dialog 
 */ 
 
extern unsigned GetGdmaChannel(void); 
/* 
 * Get GDMA channel 
 */ 
 
extern void SetUpmem2mem(void); 
/*  
 * Setup GDMA register to memory to memory transfer  
 */ 
 
 
extern void GDMARegRead(unsigned  /*channel*/); 
/* 
 * Read GDMA registers  
 */ 
 
 
extern void GDMARegWrite(unsigned  /*channel*/); 
/* 
 * Write GDMA registers  
 */ 
 
 
extern void GDMARegPrint(unsigned  /*channel*/); 
/* 
 * GDMA register display to CONSOLE 
 */ 
 
extern void GdmaTxWidth(int /*selector*/);  
/* 
 *Transfer width will be changed to 8,16,32bit  
 */             
 
extern void GdmaMem2MemTest(void); 
int GdmaMem2MemTestSub(unsigned /*GDMA Channel*/); 
/* 
 *  GDMA Memory to Memory test Module 
 */ 
 
extern void GdmaMem2Mem(unsigned  /*channel*/); 
/* 
 * GDMA memory to memory test submodule 
 */ 
 
extern void GdmaUart0Mem(void); 
extern void Uart2MemoryTest(unsigned  /*channel*/); 
extern void Uart2MemRun(unsigned /*uart ch*/, unsigned /*gdma ch*/); 
extern void GdmaUart1Mem(void); 
extern void Memory2UartTest(unsigned  /*channel*/); 
extern void Mem2UartRun(unsigned /*uart ch*/,unsigned /*gdma ch*/); 
extern void SetupUart4Gdma(unsigned /*uart ch*/,unsigned /*gdma ch*/); 
extern void SetGdmaRxReqMode(unsigned /*uart ch*/,unsigned /*gdma ch*/); 
extern void SetGdmaTxReqMode(unsigned /*uart ch*/,unsigned /*gdma ch*/); 
extern void GdmaMemInit(void * /*src*/,int /*tsize*/); 
 
extern void DataDownLoad(void); 
/*  
 * UART to Memory data transfer through GDMA continually. 
 */ 
 
extern unsigned GdmaDownLoad(void);  
/* 
 * GDMA UART versa MEMORY test module 
 */ 
 
 
extern void ExtGdmaReqTest(void); 
extern void ExtDreqRun(unsigned /*gdmachannel*/); 
/* 
 * GDMA external request test 
 */ 
 
extern void GDMAConfigView(void); 
/* 
 * GDMA Configuration viewer  
 */ 
 
extern void GdmaReset(unsigned  /*channel*/); 
/* 
 * Initialize GDMA control register  
 */ 
 
 
extern void GdmaRunEnable(unsigned  /*channel*/); 
/*  
 * GDMA Run enable /disable control 
 */ 
 
extern void GdmaIntEnable(unsigned /*gdma_channel*/); 
extern void GdmaIntDisable(unsigned /*gdma_channel*/); 
/*  
 * GDMA Run enable /disable control 
 */ 
 
extern void  GDMA0isr(void); 
extern void  GDMA1isr(void); 
/* 
 *  GDMA0, GDMA1 Interrupt Service Routines  
 */ 
 
extern void GdmaRegTest(void); 
/* 
 * GDMA Register read,write test 
 */ 
 
extern void DisplayGdma(unsigned  /*channel*/); 
extern void dcopy(U32 dmadst, U32 dmasrc,int Size, int Width) ; 
extern int DmaAutoTest(U32 src,U32 dst,int tsize,int lsize) ; 
 
#endif /* _GDMA_H_ */