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LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity pwm is 
	port( 
		a:in std_logic;	--脉宽寄存器/分频寄存器选择.1-脉宽寄存器 ,0-分频寄存器 
		countclk: in std_logic;--分频计数器计数信号 
		rs: in std_logic;--分频计数器、PWM周期计数器清零信号 
		load: in std_logic;--数据装载信号 
		dat: in std_logic_vector(7 downto 0);--8位数据输入 
		pwmout: out std_logic);--PWM信号输出 
end pwm; 
architecture work of pwm is 
	signal mycounter,cmpdat,fenpindat,fenpincount:integer range 0 to 255; 
	signal theout:std_logic; 
begin 
	dataload_block:process(load) 
	begin 
		if(load'event and load='1') then 
			if a='1' then 
				cmpdat<=conv_integer(dat); 
			else 
				fenpindat<=conv_integer(dat); 
			end if; 
		end if; 
	end process; 
	counter_block:process(countclk,rs) 
	begin 
		if (countclk'event and countclk='1') then 
			if rs='0' then 
				if fenpincount=0 then 
						fenpincount<=fenpindat; 
						mycounter<=mycounter+1; 
						if cmpdat