www.pudn.com > s3c2442_firmware.rar > Option.inc

;=========================================== 
; NAME: OPTION.inc 
; DESC: Configuration options for .S files 
; HISTORY: 
; 02.28.2002: ver 0.0 
; 03.11.2003: ver 0.0	attached for 2442. 
;=========================================== 
 
;Start address of each stacks, 
_STACK_BASEADDRESS	EQU 0x33ff8000 
_MMUTT_STARTADDRESS	EQU 0x33ff8000 
_ISR_STARTADDRESS	EQU 0x33ffff00 
 
		GBLL 	PLL_ON_START 
PLL_ON_START	SETL 	{TRUE} 
 
 
		GBLL	ENDIAN_CHANGE 
ENDIAN_CHANGE	SETL	{FALSE} 
 
		GBLA	ENTRY_BUS_WIDTH 
ENTRY_BUS_WIDTH	SETA	16 
 
 
;BUSWIDTH = 16,32 
		GBLA    BUSWIDTH	;max. bus width for the GPIO configuration 
BUSWIDTH	SETA    32 
 
 
		 
		GBLA	UCLK 
UCLK	SETA	48000000 
 
 
	GBLA	XTAL_SEL 
		GBLA	FCLK 
;(1) When xtal=12MHz 
;XTAL_SEL	SETA	12000000 
;FCLK	SETA	304000000 
;(2) When xtal=16.9344MHz 
XTAL_SEL	SETA	16934400 
FCLK	SETA	296352000 
 
 
CLKDIV_VAL	EQU	7	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6. 
 
	 
 
 [ XTAL_SEL = 12000000 
	[ FCLK = 271500000 
M_MDIV		EQU	173		;Fin=12.0MHz Fout=271.5MHz 
M_PDIV		EQU	2 
M_SDIV		EQU	2 
;M_SDIV		EQU	1		; 2442X 
	] 
	[ FCLK = 304000000 
M_MDIV		EQU	68		;Fin=12.0MHz Fout=304.8MHz 
M_PDIV		EQU	1 
M_SDIV		EQU	1 
;M_SDIV		EQU	0		; 2442X 
	] 
 
	[ UCLK = 48000000 
U_MDIV		EQU	56		;Fin=12.0MHz Fout=48MHz 
U_PDIV		EQU	2 
U_SDIV		EQU	2 
	] 
	[ UCLK = 96000000 
U_MDIV		EQU	56		;Fin=12.0MHz Fout=96MHz 
U_PDIV		EQU	2 
U_SDIV		EQU	1 
 
	] 
 
  |	; else if XTAL_SEL = 16.9344Mhz 
 
	[ FCLK = 266716800 
M_MDIV		EQU	118	;Fin=16.9344MHz 
M_PDIV		EQU	2 
M_SDIV		EQU	2	; 2442A 
;M_SDIV		EQU	1	; 2442x 
	] 
	[ FCLK = 296352000 
M_MDIV		EQU	97	;Fin=16.9344MHz 
M_PDIV		EQU	1 
M_SDIV		EQU	2	; 2442A 
;M_SDIV		EQU	1	; 2442x 
	] 
	 
	[ UCLK = 48000000 
U_MDIV		EQU	60	;Fin=16.9344MHz Fout=48MHz 
U_PDIV		EQU	4 
U_SDIV		EQU	2 
	] 
	[ UCLK = 96000000 
U_MDIV		EQU	60	;Fin=16.9344MHz Fout=96MHz 
U_PDIV		EQU	4 
U_SDIV		EQU	1 
	] 
	 
   ]	; end of if XTAL_SEL = 12000000. 
 
	END