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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity zhongbai is 
port(clk:in std_logic; 
	rst:in std_logic; 
	q:out std_logic_vector(7 downto 0)); 
end; 
architecture one of zhongbai is 
	type states is(s0,s1); 
	signal present :states; 
	signal q1:std_logic_vector(7 downto 0); 
	signal cnt:std_logic_vector(2 downto 0); 
begin 
process(clk,rst) 
begin 
if rst='1'then 
	present<=s0; 
	q1<=(others=>'0'); 
elsif clk'event and clk='1'then 
	case present is 
	when s0=>if q1="00000000"then 
		q1<="10000000"; 
		else 
			if cnt="111"then 
				cnt<=(others=>'0'); 
				q1<="00000001"; 
				present<=s1; 
			else q1<=q1(0)&q1(7 downto 1); 
				cnt<=cnt+1; 
				present<=s0; 
			end if; 
		end if; 
	when s1=>if cnt="111"then 
			cnt<=(others=>'0'); 
			q1<="10000000"; 
			present<=s0; 
		else q1<=q1(6 downto 0)&q1(7); 
			cnt<=cnt+1; 
			present<=s1; 
		end if; 
	end case; 
end if; 
end process; 
q<=q1; 
end;