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library ieee; 
use ieee.std_logic_1164.all; 
entity class is 
port ( a : in std_logic_vector(23 downto 0); 
        b : out std_logic); 
end; 
architecture one of class is 
begin 
process(a) 
begin 
case a  is 
when "000001110100100101011001" => b <= '1'; 
when "000010000100100101011001" => b <= '1'; 
when "000010000101100101011001" => b <= '1'; 
when "000010010011100101011001" => b <= '1'; 
when "000100000001100101011001" => b <= '1'; 
when "000100010000010001011001" => b <= '1'; 
when "000100010100100101011001" => b <= '1'; 
when "000101000101010001011001" => b <= '1'; 
when "000101010011100101011001" => b <= '1'; 
when "000101100011010001011001" => b <= '1'; 
when "000101100100010001011001" => b <= '1'; 
when "000101110010100101011001" => b <= '1'; 
when others  => null; 
end case; 
end process; 
end;