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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity c6 is 
    Port ( clk : in std_logic; 
          dout : out std_logic_vector(3 downto 0)); 
end c6; 
architecture Behavioral of c6 is 
   signal count : std_logic_vector(3 downto 0); 
begin 
	process(clk) 
	begin 
	   if rising_edge(clk) then 
		   if count = "0101" then 
			   count <= "0000"; 
           else  
			   count <= count+1; 
           end if; 
      end if; 
    dout <= count; 
    end process; 
end Behavioral;