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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity c24 is 
    Port ( clk : in std_logic; 
         dout : out std_logic_vector(7 downto 0)); 
end c24; 
architecture Behavioral of c24 is 
signal count : std_logic_vector(7 downto 0); 
begin 
	process(clk) 
	begin 
	   if rising_edge(clk) then	    
		   if count(3 downto 0)="1001" then 
			 count(3 downto 0)<="0000"; 
			count(5 downto 4)<=count(5 downto 4) +1; 
         else 
			count(3 downto 0)<=count(3 downto 0)+1; 
         end if; 
		 if count="00100011" then 
		   count<="00000000"; 
         end if; 
      end if; 
    dout <= count; 
   end process; 
end Behavioral;